Using Multiple Clocks in Highlevel Synthesis to overcome unbalanced clock cycles

High-level Synthesis (HLS) is a technique to compile C/C++ algorithmic code directly to hardware circuits (Verilog/VHDL). Typically, HLS schedulers partition the graph of operations to layers L₁,L₂, ⋯, L_k where the operations in each layer are executed in consecutive clock cycles. The execution time for each layer could be different, leading to unbalanced cycles because cannot ensure finding optimal clock-width by finding a common divisor between the layer's execution time. Previous works like Re-clocking and Chaining attempt to balance the scheduling layers by moving operations from proceeding layers to the current one, optimizing clock latency, and finding optimal clock-width. However, unlike to solution proposed here, these techniques may sometimes fail to obtain the optimal solution because they cannot ensure finding a common divisor between the layer's execution time. The proposed technique is to use separate overlapping clocks clk₁,clk₂, ⋯, clk_k for each layer wherein the 0 → 1 transion in each clk_i occures at Σ latency({L_j) | L_j} ∈ (longest path to L_i). and 1 → 0 transition in each clk_i occurs at (Σ latency({L_j) | L_j} ∈ (longest path to L_i) + L_ilatency In this way, the time-waists of unbalanced latencies disappear into an optimal common clock period of each clk_i for straight line code, and statistically near the optimal for non-straight line code. A second contribution of this work is an extension of this technique to perform global scheduling, i.e., obtain balanced layers for multiple basic blocks of a full control-flow graph (e.g., a combination of nested-loops and conditional statements). This technique was implemented in the LLVM compiler. Results suggest significant improvements in execution time and power compared to a commercial HLS tool (Vitis).