Abstract
Relaxing the sequential specification of shared objects has been proposed as a promising approach to obtain implementations with better complexity. In this paper, we study the step complexity of relaxed variants of two common shared objects: max registers and counters. In particular, we consider the k-multiplicative-accurate max register and the k-multiplicative-accurate counter, where read operations are allowed to err by a multiplicative factor of k (for some k∈N). More accurately, reads are allowed to return an approximate value x of the maximum value v previously written to the max register, or of the number v of increments previously applied to the counter, respectively, such that v/k≤x≤v⋅k. We provide upper and lower bounds on the complexity of implementing these objects in a wait-free manner in the shared memory model.
| Original language | American English |
|---|---|
| Title of host publication | Proceedings - 2021 IEEE 41st International Conference on Distributed Computing Systems, ICDCS 2021 |
| Pages | 438-448 |
| Number of pages | 11 |
| ISBN (Electronic) | 9781665445139 |
| DOIs | |
| State | Published - 4 Oct 2021 |
| Event | 41st IEEE International Conference on Distributed Computing Systems, ICDCS 2021 - Virtual, Washington, United States Duration: 7 Jul 2021 → 10 Jul 2021 |
Conference
| Conference | 41st IEEE International Conference on Distributed Computing Systems, ICDCS 2021 |
|---|---|
| Country/Territory | United States |
| City | Virtual, Washington |
| Period | 7/07/21 → 10/07/21 |
Keywords
- Concurrent data structures
- Distributed algorithms
- Distributed computing
- Fault tolerance
- Relaxed specifications
- Shared memory
All Science Journal Classification (ASJC) codes
- Software
- Hardware and Architecture
- Computer Networks and Communications
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