@inproceedings{0cf18c8bc4644b7f8a65b7583d53fd86,
title = "Unifying wire and time scheduling for highlevel synthesis",
abstract = "Wire scaling is becoming problematic for semi-global and global wires in sub 40nm ASIC/VLSI chips. We propose an algorithm that simultaneously minimizes the time T and wire-lengths W for highlevel synthesis from C to Verilog. The program is compiled to a graphs G of arithmetic/logical and memory operations. We developed a formal model wherein the optimal product W × T of a given G can be resolved. The proposed algorithm for general Gs works by recursively decomposing G to either grid-like or tree-like induced sub-graphs and combines their optimal solutions. We have implemented this algorithm in the LLVM compiler and obtained an HLS compiler that successfully minimizes both W × T of the resulting circuits.",
keywords = "Highlevel synthesis, Scheduling, Wire-area",
author = "{Ben Asher}, Yosi and Irina Lipov",
note = "Publisher Copyright: {\textcopyright} 2018 IEEE.; 12th IEEE International Symposium on Embedded Multicore/Many-Core Systems-on-Chip, MCSoC 2018 ; Conference date: 12-09-2018 Through 14-09-2018",
year = "2018",
month = nov,
day = "16",
doi = "https://doi.org/10.1109/MCSoC2018.2018.00017",
language = "American English",
series = "Proceedings - 2018 IEEE 12th International Symposium on Embedded Multicore/Many-Core Systems-on-Chip, MCSoC 2018",
publisher = "Institute of Electrical and Electronics Engineers Inc.",
pages = "28--35",
booktitle = "Proceedings - 2018 IEEE 12th International Symposium on Embedded Multicore/Many-Core Systems-on-Chip, MCSoC 2018",
address = "United States",
}