Towards Hazard-Free Multiplexer Based Implementation of Self-Timed Circuits

Alexander Kushnerov; Moti Medina; Alexandre Yakovlev

doi:10.1109/ASYNC48570.2021.00011

Towards Hazard-Free Multiplexer Based Implementation of Self-Timed Circuits

Alexander Kushnerov, Moti Medina, Alexandre Yakovlev

Ben-Gurion University of the Negev, Bar-Ilan University

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

Abstract

The cost of design, test and fabrication of self-timed circuits remains prohibitive for their wider adoption in practice. Addressing this issue, researchers are trying to find ways for rapid prototyping of self-timed circuits in FPGAs. Combinational logic is realized in FPGAs by look-up tables (LUTs), which are typically built as a binary tree of 2-way multiplexers (MUX 2:1). This brings us to the idea of using MUX 2:1 in self-timed designs particularly, in quasi-delay-insensitive (QDI) circuits. Multiplexers however, realize a binate (non-monotone) Boolean function and therefore may cause logic hazards. A standard way for preventing these hazards requires designing of special circuit for MUX 2:1. On the other hand, there are indirect evidences that the multiplexers in some commercial FPGAs are hazard-free. Based on this assumption, we propose an original approach for realizing a multi-input C-element, which is widely used in QDI circuits. This paves the way for using hazard-free MUX 2:1 in more complex self-timed elements. All the proposed circuits are designed and verified in a CAD tool Workcraft.

Original language	American English
Title of host publication	Proceedings - 27th IEEE International Symposium on Asynchronous Circuits and Systems, ASYNC 2021
Pages	17-24
Number of pages	8
ISBN (Electronic)	9781728141329
DOIs	https://doi.org/10.1109/ASYNC48570.2021.00011
State	Published - 1 Jan 2021
Event	27th IEEE International Symposium on Asynchronous Circuits and Systems, ASYNC 2021 - Virtual, Online, China Duration: 7 Sep 2021 → 10 Sep 2021

Publication series

Name	Proceedings - International Symposium on Asynchronous Circuits and Systems
Volume	2021-September

Conference

Conference	27th IEEE International Symposium on Asynchronous Circuits and Systems, ASYNC 2021
Country/Territory	China
City	Virtual, Online
Period	7/09/21 → 10/09/21

UN SDGs

This output contributes to the following UN Sustainable Development Goals (SDGs)

SDG 9 Industry, Innovation, and Infrastructure

Keywords

Binate function
C-element
Consensus cube
Hazard
Lookup table
Multiplexer
QDI circuit

All Science Journal Classification (ASJC) codes

Electrical and Electronic Engineering

Access to Document

10.1109/ASYNC48570.2021.00011

Cite this

Kushnerov, A., Medina, M., & Yakovlev, A. (2021). Towards Hazard-Free Multiplexer Based Implementation of Self-Timed Circuits. In Proceedings - 27th IEEE International Symposium on Asynchronous Circuits and Systems, ASYNC 2021 (pp. 17-24). (Proceedings - International Symposium on Asynchronous Circuits and Systems; Vol. 2021-September). https://doi.org/10.1109/ASYNC48570.2021.00011

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title = "Towards Hazard-Free Multiplexer Based Implementation of Self-Timed Circuits",

abstract = "The cost of design, test and fabrication of self-timed circuits remains prohibitive for their wider adoption in practice. Addressing this issue, researchers are trying to find ways for rapid prototyping of self-timed circuits in FPGAs. Combinational logic is realized in FPGAs by look-up tables (LUTs), which are typically built as a binary tree of 2-way multiplexers (MUX 2:1). This brings us to the idea of using MUX 2:1 in self-timed designs particularly, in quasi-delay-insensitive (QDI) circuits. Multiplexers however, realize a binate (non-monotone) Boolean function and therefore may cause logic hazards. A standard way for preventing these hazards requires designing of special circuit for MUX 2:1. On the other hand, there are indirect evidences that the multiplexers in some commercial FPGAs are hazard-free. Based on this assumption, we propose an original approach for realizing a multi-input C-element, which is widely used in QDI circuits. This paves the way for using hazard-free MUX 2:1 in more complex self-timed elements. All the proposed circuits are designed and verified in a CAD tool Workcraft.",

keywords = "Binate function, C-element, Consensus cube, Hazard, Lookup table, Multiplexer, QDI circuit",

author = "Alexander Kushnerov and Moti Medina and Alexandre Yakovlev",

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Kushnerov, A, Medina, M & Yakovlev, A 2021, Towards Hazard-Free Multiplexer Based Implementation of Self-Timed Circuits. in Proceedings - 27th IEEE International Symposium on Asynchronous Circuits and Systems, ASYNC 2021. Proceedings - International Symposium on Asynchronous Circuits and Systems, vol. 2021-September, pp. 17-24, 27th IEEE International Symposium on Asynchronous Circuits and Systems, ASYNC 2021, Virtual, Online, China, 7/09/21. https://doi.org/10.1109/ASYNC48570.2021.00011

Towards Hazard-Free Multiplexer Based Implementation of Self-Timed Circuits. / Kushnerov, Alexander; Medina, Moti; Yakovlev, Alexandre.
Proceedings - 27th IEEE International Symposium on Asynchronous Circuits and Systems, ASYNC 2021. 2021. p. 17-24 (Proceedings - International Symposium on Asynchronous Circuits and Systems; Vol. 2021-September).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

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AU - Medina, Moti

AU - Yakovlev, Alexandre

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N2 - The cost of design, test and fabrication of self-timed circuits remains prohibitive for their wider adoption in practice. Addressing this issue, researchers are trying to find ways for rapid prototyping of self-timed circuits in FPGAs. Combinational logic is realized in FPGAs by look-up tables (LUTs), which are typically built as a binary tree of 2-way multiplexers (MUX 2:1). This brings us to the idea of using MUX 2:1 in self-timed designs particularly, in quasi-delay-insensitive (QDI) circuits. Multiplexers however, realize a binate (non-monotone) Boolean function and therefore may cause logic hazards. A standard way for preventing these hazards requires designing of special circuit for MUX 2:1. On the other hand, there are indirect evidences that the multiplexers in some commercial FPGAs are hazard-free. Based on this assumption, we propose an original approach for realizing a multi-input C-element, which is widely used in QDI circuits. This paves the way for using hazard-free MUX 2:1 in more complex self-timed elements. All the proposed circuits are designed and verified in a CAD tool Workcraft.

AB - The cost of design, test and fabrication of self-timed circuits remains prohibitive for their wider adoption in practice. Addressing this issue, researchers are trying to find ways for rapid prototyping of self-timed circuits in FPGAs. Combinational logic is realized in FPGAs by look-up tables (LUTs), which are typically built as a binary tree of 2-way multiplexers (MUX 2:1). This brings us to the idea of using MUX 2:1 in self-timed designs particularly, in quasi-delay-insensitive (QDI) circuits. Multiplexers however, realize a binate (non-monotone) Boolean function and therefore may cause logic hazards. A standard way for preventing these hazards requires designing of special circuit for MUX 2:1. On the other hand, there are indirect evidences that the multiplexers in some commercial FPGAs are hazard-free. Based on this assumption, we propose an original approach for realizing a multi-input C-element, which is widely used in QDI circuits. This paves the way for using hazard-free MUX 2:1 in more complex self-timed elements. All the proposed circuits are designed and verified in a CAD tool Workcraft.

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M3 - Conference contribution

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BT - Proceedings - 27th IEEE International Symposium on Asynchronous Circuits and Systems, ASYNC 2021

T2 - 27th IEEE International Symposium on Asynchronous Circuits and Systems, ASYNC 2021

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ER -

Towards Hazard-Free Multiplexer Based Implementation of Self-Timed Circuits

Abstract

Publication series

Conference

UN SDGs

Keywords

All Science Journal Classification (ASJC) codes

Access to Document

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Cite this