TY - GEN
T1 - Towards Hazard-Free Multiplexer Based Implementation of Self-Timed Circuits
AU - Kushnerov, Alexander
AU - Medina, Moti
AU - Yakovlev, Alexandre
N1 - Publisher Copyright: © 2021 IEEE
PY - 2021/1/1
Y1 - 2021/1/1
N2 - The cost of design, test and fabrication of self-timed circuits remains prohibitive for their wider adoption in practice. Addressing this issue, researchers are trying to find ways for rapid prototyping of self-timed circuits in FPGAs. Combinational logic is realized in FPGAs by look-up tables (LUTs), which are typically built as a binary tree of 2-way multiplexers (MUX 2:1). This brings us to the idea of using MUX 2:1 in self-timed designs particularly, in quasi-delay-insensitive (QDI) circuits. Multiplexers however, realize a binate (non-monotone) Boolean function and therefore may cause logic hazards. A standard way for preventing these hazards requires designing of special circuit for MUX 2:1. On the other hand, there are indirect evidences that the multiplexers in some commercial FPGAs are hazard-free. Based on this assumption, we propose an original approach for realizing a multi-input C-element, which is widely used in QDI circuits. This paves the way for using hazard-free MUX 2:1 in more complex self-timed elements. All the proposed circuits are designed and verified in a CAD tool Workcraft.
AB - The cost of design, test and fabrication of self-timed circuits remains prohibitive for their wider adoption in practice. Addressing this issue, researchers are trying to find ways for rapid prototyping of self-timed circuits in FPGAs. Combinational logic is realized in FPGAs by look-up tables (LUTs), which are typically built as a binary tree of 2-way multiplexers (MUX 2:1). This brings us to the idea of using MUX 2:1 in self-timed designs particularly, in quasi-delay-insensitive (QDI) circuits. Multiplexers however, realize a binate (non-monotone) Boolean function and therefore may cause logic hazards. A standard way for preventing these hazards requires designing of special circuit for MUX 2:1. On the other hand, there are indirect evidences that the multiplexers in some commercial FPGAs are hazard-free. Based on this assumption, we propose an original approach for realizing a multi-input C-element, which is widely used in QDI circuits. This paves the way for using hazard-free MUX 2:1 in more complex self-timed elements. All the proposed circuits are designed and verified in a CAD tool Workcraft.
KW - Binate function
KW - C-element
KW - Consensus cube
KW - Hazard
KW - Lookup table
KW - Multiplexer
KW - QDI circuit
UR - http://www.scopus.com/inward/record.url?scp=85126097617&partnerID=8YFLogxK
U2 - https://doi.org/10.1109/ASYNC48570.2021.00011
DO - https://doi.org/10.1109/ASYNC48570.2021.00011
M3 - Conference contribution
T3 - Proceedings - International Symposium on Asynchronous Circuits and Systems
SP - 17
EP - 24
BT - Proceedings - 27th IEEE International Symposium on Asynchronous Circuits and Systems, ASYNC 2021
T2 - 27th IEEE International Symposium on Asynchronous Circuits and Systems, ASYNC 2021
Y2 - 7 September 2021 through 10 September 2021
ER -
