TY - GEN
T1 - Towards a memristive hardware secure hash function (MemHash)
AU - Azriel, Leonid
AU - Kvatinsky, Shahar
N1 - Publisher Copyright: © 2017 IEEE.
PY - 2017/6/16
Y1 - 2017/6/16
N2 - Hardware based hash functions might provide a low cost and low power alternative to the classic solutions, which are based on implementations of mathematical cryptographic algorithms. In this paper, we propose MemHash, a hardware secure hash function built using memristive technology that exploits the unique properties of memristors. The MemHash operation is based on intrinsic device characteristics. Furthermore, it exploits process variations for implicit key embedding, thus creating a keyed-hash message authentication code (HMAC) that does not involve a separate key generation and management process. MemHash comprises a memristive crossbar with a differential read mechanism and a scrambler unit. The scrambler unit receives the input message as a bit stream and digitally mixes it with data read from the array. For every bit of the message, the scrambler generates a write address and a value to perform a single-cell write cycle to the crossbar. Because the crossbar is designed to be extremely sensitive to the write disturb phenomenon, every single-cell write alters additional cells in the design, thus increasing the entropy. The differential read mechanism provides sensitivity to process variations and robustness in operating conditions, yielding a PUF-like effect. MemHash is evaluated with a 16 × 16 memristive crossbar structure. Our simulation results demonstrate the statistical characteristics of the proposed design, showing close-to-optimal uniqueness and diffuseness.
AB - Hardware based hash functions might provide a low cost and low power alternative to the classic solutions, which are based on implementations of mathematical cryptographic algorithms. In this paper, we propose MemHash, a hardware secure hash function built using memristive technology that exploits the unique properties of memristors. The MemHash operation is based on intrinsic device characteristics. Furthermore, it exploits process variations for implicit key embedding, thus creating a keyed-hash message authentication code (HMAC) that does not involve a separate key generation and management process. MemHash comprises a memristive crossbar with a differential read mechanism and a scrambler unit. The scrambler unit receives the input message as a bit stream and digitally mixes it with data read from the array. For every bit of the message, the scrambler generates a write address and a value to perform a single-cell write cycle to the crossbar. Because the crossbar is designed to be extremely sensitive to the write disturb phenomenon, every single-cell write alters additional cells in the design, thus increasing the entropy. The differential read mechanism provides sensitivity to process variations and robustness in operating conditions, yielding a PUF-like effect. MemHash is evaluated with a 16 × 16 memristive crossbar structure. Our simulation results demonstrate the statistical characteristics of the proposed design, showing close-to-optimal uniqueness and diffuseness.
UR - http://www.scopus.com/inward/record.url?scp=85025150427&partnerID=8YFLogxK
U2 - 10.1109/HST.2017.7951797
DO - 10.1109/HST.2017.7951797
M3 - منشور من مؤتمر
T3 - Proceedings of the 2017 IEEE International Symposium on Hardware Oriented Security and Trust, HOST 2017
SP - 51
EP - 55
BT - Proceedings of the 2017 IEEE International Symposium on Hardware Oriented Security and Trust, HOST 2017
T2 - 10th IEEE International Symposium on Hardware Oriented Security and Trust, HOST 2017
Y2 - 1 May 2017 through 5 May 2017
ER -