Towards a DML Optimized Synthesis

Itamar Levi; Alexander Fish

doi:10.1007/978-3-030-40786-5_8

Towards a DML Optimized Synthesis

Itamar Levi, Alexander Fish

Bar-Ilan University

Research output: Chapter in Book/Report/Conference proceeding › Chapter

Abstract

In the previous chapter we discussed ways how to characterize DML cells into several libraries and use these with standard EDA tools. In this chapter we outline an optimized synthesis procedure for DML design. In a nutshell, this methodology involves changing certain...

Original language	English
Title of host publication	Dual Mode Logic
Place of Publication	Cham, Switzerland
Pages	143-155
Number of pages	13
DOIs	https://doi.org/10.1007/978-3-030-40786-5_8
State	Published - 16 Dec 2020

Keywords

ASIC
Automation
Characterization
Constraints
Correct precharge (CPC)
DML
DML synthesis
Electronic design automation (EDA)
Footed gates (FG)
Gate level (GTL)
Glitching
Hardware description language (HDL)
ISCAS benchmarks
Liberty
Perl
Post-synthesis
Pseudo-static
RTL-synthesis
Single transition requirement (STR)
Standard cell library
Standard flow
Static timing analysis (STA)

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10.1007/978-3-030-40786-5_8

Cite this

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KW - Automation

KW - Characterization

KW - Constraints

KW - Correct precharge (CPC)

KW - DML

KW - DML synthesis

KW - Electronic design automation (EDA)

KW - Footed gates (FG)

KW - Gate level (GTL)

KW - Glitching

KW - Hardware description language (HDL)

KW - ISCAS benchmarks

KW - Liberty

KW - Perl

KW - Post-synthesis

KW - Pseudo-static

KW - RTL-synthesis

KW - Single transition requirement (STR)

KW - Standard cell library

KW - Standard flow

KW - Static timing analysis (STA)

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DO - 10.1007/978-3-030-40786-5_8

M3 - فصل

SP - 143

EP - 155

BT - Dual Mode Logic

CY - Cham, Switzerland

ER -

Towards a DML Optimized Synthesis

Abstract

Keywords

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