Towards a DML Library Characterization and Design with Standard Flow

Itamar Levi; Alexander Fish

doi:https://doi.org/10.1007/978-3-030-40786-5_7

Towards a DML Library Characterization and Design with Standard Flow

Itamar Levi, Alexander Fish

Bar-Ilan University

Research output: Chapter in Book/Report/Conference proceeding › Chapter

Abstract

After discussing the DML foundations and presenting several conceptual use cases of DML, we now introduce the reader to ways to scale up the utilization space of DML. Specifically, this chapter presents an approach to a DML cell-library characterization and describes...

Original language	English
Title of host publication	Dual Mode Logic
Place of Publication	Cham, Switzerland
Pages	115-142
Number of pages	28
DOIs	https://doi.org/10.1007/978-3-030-40786-5_7
State	Published - 16 Dec 2020

Keywords

ASIC
Area expansion
Automation
Cadence
Cascading
Characterization
Connection class
Crossed cells
DML
DML synthesis
Dummy cells
Duplication
Electronic design automation (EDA)
Footless
Gate count
Liberty
Mapping
Monotonicity
Non-unate
Post-synthesis
Pseudo-static
RTL-synthesis
Semi-footed cells
Slowdown
Speedup
Standard cell library
Standard flow
Static timing analysis (STA)
Synopsis
Violation

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Cite this

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title = "Towards a DML Library Characterization and Design with Standard Flow",

abstract = "After discussing the DML foundations and presenting several conceptual use cases of DML, we now introduce the reader to ways to scale up the utilization space of DML. Specifically, this chapter presents an approach to a DML cell-library characterization and describes...",

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AU - Fish, Alexander

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KW - ASIC

KW - Area expansion

KW - Automation

KW - Cadence

KW - Cascading

KW - Characterization

KW - Connection class

KW - Crossed cells

KW - DML

KW - DML synthesis

KW - Dummy cells

KW - Duplication

KW - Electronic design automation (EDA)

KW - Footless

KW - Gate count

KW - Liberty

KW - Mapping

KW - Monotonicity

KW - Non-unate

KW - Post-synthesis

KW - Pseudo-static

KW - RTL-synthesis

KW - Semi-footed cells

KW - Slowdown

KW - Speedup

KW - Standard cell library

KW - Standard flow

KW - Static timing analysis (STA)

KW - Synopsis

KW - Violation

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U2 - https://doi.org/10.1007/978-3-030-40786-5_7

DO - https://doi.org/10.1007/978-3-030-40786-5_7

M3 - فصل

SP - 115

EP - 142

BT - Dual Mode Logic

CY - Cham, Switzerland

ER -

Towards a DML Library Characterization and Design with Standard Flow

Abstract

Keywords

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