The Triejax architecture: Accelerating graph operations through relational joins

Research output: Chapter in Book/Report/Conference proceedingConference contributionpeer-review

Abstract

Graph pattern matching (e.g., finding all cycles and cliques) has become an important component in domains such as social networks, biology and cyber-security. In recent years, the database community has shown that graph pattern matching problems can be mapped to an efficient new class of relational join algorithms. In this paper, we argue that this new class of join algorithms is highly amenable to specialized hardware acceleration thanks to two fundamental properties: improved memory locality and inherent concurrency. The improved locality is a result of the bound number of intermediate results these algorithms generate, which yields smaller working sets. Coupled with custom caching mechanisms, this property can be used to dramatically reduce the number of main memory accesses invoked by the algorithm. In addition, their inherent concurrency can be leveraged for effective hardware acceleration and hiding memory latency. We demonstrate the hardware amenability of this new class of algorithms by introducing TrieJax, a hardware accelerator for graph pattern matching that can be tightly integrated into existing manycore processors. TrieJax employs custom caching mechanisms and a massively multithreaded design to dramatically accelerate graph pattern matching. We evaluate TrieJax on a set standard graph pattern matching queries and datasets. Our evaluation shows that TrieJax outperforms recently proposed hardware accelerators for graph and database processing that do not employ the new class of algorithms by 7 - 63× on average (up to 539×), while consuming 15 - 179× less energy (up to 1750×), and systems that incorporate modern relational join algorithms by 9 - 20× on average (up to 45×), while consuming 59 - 110× less energy (up to 372×).

Original languageEnglish
Title of host publicationASPLOS 2020 - 25th International Conference on Architectural Support for Programming Languages and Operating Systems
Pages1217-1231
Number of pages15
ISBN (Electronic)9781450371025
DOIs
StatePublished - 9 Mar 2020
Event25th International Conference on Architectural Support for Programming Languages and Operating Systems, ASPLOS 2020 - Lausanne, Switzerland
Duration: 16 Mar 202020 Mar 2020

Publication series

NameInternational Conference on Architectural Support for Programming Languages and Operating Systems - ASPLOS

Conference

Conference25th International Conference on Architectural Support for Programming Languages and Operating Systems, ASPLOS 2020
Country/TerritorySwitzerland
CityLausanne
Period16/03/2020/03/20

Keywords

  • Algorithmic design
  • Databases
  • Graph analytics
  • Hardware
  • Hardware acceleration
  • Relational join

All Science Journal Classification (ASJC) codes

  • Software
  • Information Systems
  • Hardware and Architecture

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