Temperature and process compensated clock generator using feedback TPC bias

Tzung Je Lee, Doron Shmilovitz, Yi Jie Hsieh, Chua Chin Wang

Research output: Chapter in Book/Report/Conference proceedingConference contributionpeer-review

Abstract

This paper proposes a temperature and process compensated clock generator using a feedback TPC (temperature and process compensation) bias circuit. With the proposed feedback TPC bias based on the OPA, MOS transistors and resistors, the BJT required in traditional bandgap bias circuit could be avoided. Thus, it is easy to be integrated with less area penalty. The proposed design is implemented using 0.25μm BCD process. According to the all-corners simulation results, the proposed clock generator processes the frequency diffusion error of 2.10% in the worst cases. Besides, the worst case duty cycle is simulated to be 48.93.%. The area of the chip is 0.1356 mm 2.

Original languageEnglish
Title of host publicationICICDT 2012 - IEEE International Conference on Integrated Circuit Design and Technology
DOIs
StatePublished - 2012
EventIEEE International Conference on Integrated Circuit Design and Technology, ICICDT 2012 - Austin, TX, United States
Duration: 30 May 20121 Jun 2012

Publication series

NameICICDT 2012 - IEEE International Conference on Integrated Circuit Design and Technology

Conference

ConferenceIEEE International Conference on Integrated Circuit Design and Technology, ICICDT 2012
Country/TerritoryUnited States
CityAustin, TX
Period30/05/121/06/12

Keywords

  • Clock generator
  • compensation
  • process
  • temperature

All Science Journal Classification (ASJC) codes

  • Hardware and Architecture
  • Electrical and Electronic Engineering

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