System, Method, and Circuitry for Blind Timing Mismatch Estimation of Interleaved Analog-to-Digital Converters

Naor Goldman (Inventor), Noam Tal (Inventor), Yonina C. Eldar (Inventor), Charles Sestok (Inventor), Efrat Levy (Inventor)

Research output: Patent

Abstract

A timing skew estimation system is disclosed that includes a plurality of interleaved analog-to-digital converter circuits (ADCs), a timing mismatch estimation unit, and a correction unit. The timing mismatch estimation unit calculates a correlation between each of the plurality of ADCs. Then the timing mismatch estimation unit calculates a cost function for each of the plurality of ADCs, except the reference ADC. The timing mismatch estimation unit further calculates a gradient for each of the plurality of ADCs, except the reference ADC. The timing mismatch estimation unit also continually calculates the timing skew of each of the plurality of ADCs, except the reference ADC, as the sum of an immediately previous estimate of the timing skew of each ADC, except the reference ADC, and a product of a function of the gradient of each of the plurality of ADCs, except the reference ADC, and a step size, The correction unit continually corrects the output of each of the plurality of ADCs, except the reference ADC, based on the estimates of the timing skew of each of the plurality of ADCs, except the reference ADC. Eventually, the timing skew estimation system determines a converged estimate of the timing skew of each of the plurality of ADCs, except the reference ADC. A method of estimating timing skew and timing skew estimation circuitry are also disclosed.
Original languageEnglish
Patent numberUS20120050079A1, US8159377B2
Priority date31/08/10
StatePublished - 1 Mar 2012

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