Silicon Evaluation of Multimode Dual Mode Logic for PVT-Aware Datapaths

Inbal Stanger; Netanel Shavit; Ramiro Taco; Marco Lanuzza; Alexander Fish

doi:10.1109/tcsii.2020.3013331

Silicon Evaluation of Multimode Dual Mode Logic for PVT-Aware Datapaths

Inbal Stanger, Netanel Shavit, Ramiro Taco, Marco Lanuzza, Alexander Fish

Bar-Ilan University

Research output: Contribution to journal › Article › peer-review

Abstract

This brief presents the unique capabilities of the multimode Dual Mode Logic (DML) design technique to define run-time adaptive datapaths to overcome process and environmental (i.e., temperature and voltage) variations. A proof-of-concept benchmark circuit is designed and fabricated in 65 nm technology. Measurements on 10 test chips, while considering supply voltages spanning 0.6V to 1.2V and temperature variations ranging from -40 °C to 125 °C confirm the effectiveness of this approach to compensate for severe process, voltage and temperature (PVT) variations.

Original language	English
Article number	9153856
Pages (from-to)	1639-1643
Number of pages	5
Journal	IEEE Transactions on Circuits and Systems II: Express Briefs
Volume	67
Issue number	9
DOIs	https://doi.org/10.1109/tcsii.2020.3013331
State	Published - 1 Sep 2020

Keywords

Dual mode logic (DML)
PVT variation tolerance
adaptive circuits

All Science Journal Classification (ASJC) codes

Electrical and Electronic Engineering

Access to Document

10.1109/tcsii.2020.3013331

Cite this

@article{9b5335b03c234c36b76701c1d068d475,

title = "Silicon Evaluation of Multimode Dual Mode Logic for PVT-Aware Datapaths",

abstract = "This brief presents the unique capabilities of the multimode Dual Mode Logic (DML) design technique to define run-time adaptive datapaths to overcome process and environmental (i.e., temperature and voltage) variations. A proof-of-concept benchmark circuit is designed and fabricated in 65 nm technology. Measurements on 10 test chips, while considering supply voltages spanning 0.6V to 1.2V and temperature variations ranging from -40 °C to 125 °C confirm the effectiveness of this approach to compensate for severe process, voltage and temperature (PVT) variations.",

keywords = "Dual mode logic (DML), PVT variation tolerance, adaptive circuits",

author = "Inbal Stanger and Netanel Shavit and Ramiro Taco and Marco Lanuzza and Alexander Fish",

note = "Publisher Copyright: {\textcopyright} 2004-2012 IEEE.",

year = "2020",

month = sep,

day = "1",

doi = "10.1109/tcsii.2020.3013331",

language = "الإنجليزيّة",

volume = "67",

pages = "1639--1643",

journal = "IEEE Transactions on Circuits and Systems II: Express Briefs",

issn = "1549-7747",

number = "9",

}

TY - JOUR

T1 - Silicon Evaluation of Multimode Dual Mode Logic for PVT-Aware Datapaths

AU - Stanger, Inbal

AU - Shavit, Netanel

AU - Taco, Ramiro

AU - Lanuzza, Marco

AU - Fish, Alexander

PY - 2020/9/1

Y1 - 2020/9/1

N2 - This brief presents the unique capabilities of the multimode Dual Mode Logic (DML) design technique to define run-time adaptive datapaths to overcome process and environmental (i.e., temperature and voltage) variations. A proof-of-concept benchmark circuit is designed and fabricated in 65 nm technology. Measurements on 10 test chips, while considering supply voltages spanning 0.6V to 1.2V and temperature variations ranging from -40 °C to 125 °C confirm the effectiveness of this approach to compensate for severe process, voltage and temperature (PVT) variations.

AB - This brief presents the unique capabilities of the multimode Dual Mode Logic (DML) design technique to define run-time adaptive datapaths to overcome process and environmental (i.e., temperature and voltage) variations. A proof-of-concept benchmark circuit is designed and fabricated in 65 nm technology. Measurements on 10 test chips, while considering supply voltages spanning 0.6V to 1.2V and temperature variations ranging from -40 °C to 125 °C confirm the effectiveness of this approach to compensate for severe process, voltage and temperature (PVT) variations.

KW - Dual mode logic (DML)

KW - PVT variation tolerance

KW - adaptive circuits

UR - http://www.scopus.com/inward/record.url?scp=85090857156&partnerID=8YFLogxK

U2 - 10.1109/tcsii.2020.3013331

DO - 10.1109/tcsii.2020.3013331

M3 - مقالة

SN - 1549-7747

VL - 67

SP - 1639

EP - 1643

JO - IEEE Transactions on Circuits and Systems II: Express Briefs

JF - IEEE Transactions on Circuits and Systems II: Express Briefs

IS - 9

M1 - 9153856

ER -

Silicon Evaluation of Multimode Dual Mode Logic for PVT-Aware Datapaths

Abstract

Keywords

All Science Journal Classification (ASJC) codes

Access to Document

Other files and links

Fingerprint

Cite this