@inproceedings{82d3a3b92170415bb7b5da66bf4dedbf,
title = "SerOpt: Transistor Sizing Algorithm and Optimization Utility for Minimizing Soft Error Rate",
abstract = "This paper presents a transistor sizing algorithm and utility for soft-error (SER) protection circuits. The algorithm applies a gradient-descent convergence scheme for rapidly calculating an optimized sizing configuration per specific protection circuit instance. The utility efficiently interacts with commercial SPICE circuit-level tools for highest accuracy. The analysis and optimization flow is distributed over parallel compute resources to provide a scalable and feasible solution for large designs. The solution is demonstrated on two configurations of the Muller C-element circuit, a widely used component for SER protection across designs. By sizing the test circuits with the proposed utility, a SER protection improvement of as much as two orders-of-magnitude is achieved over a baseline design within minutes of compute runtime.",
author = "Yehuda Kra and Yoav Weitzman and Adam Teman",
note = "Publisher Copyright: {\textcopyright} 2022 IEEE.; 37th Conference on Design of Circuits and Integrated Systems, DCIS 2022 ; Conference date: 16-11-2022 Through 18-11-2022",
year = "2022",
month = jan,
day = "1",
doi = "10.1109/dcis55711.2022.9970146",
language = "الإنجليزيّة",
series = "DCIS 2022 - Proceedings of the 37th Conference on Design of Circuits and Integrated Systems",
publisher = "Institute of Electrical and Electronics Engineers Inc.",
booktitle = "DCIS 2022 - Proceedings of the 37th Conference on Design of Circuits and Integrated Systems",
address = "الولايات المتّحدة",
}