Refresh Algorithm for Ensuring 100% Memory Availability in Gain-Cell Embedded DRAM Macros

Gain-cell embedded DRAM (GC-eDRAM) is a dense, low power option for embedded memory implementation, supporting low supply voltages; however, it suffers from limited data retention time (DRT) and requires periodic refresh operations, limiting its use only to applications that can tolerate temporary memory blockages. In this work we propose a memory architecture based on a novel refreshing algorithm that provides 100% memory availability for the user, resulting in no performance loss for any possible access pattern. This approach allows the memory to have a standard SRAM interface ('vanilla interface'), supporting direct replacement of the SRAM memory with a GC-eDRAM memory. The algorithm/architecture was implemented in a 65 nm CMOS technology resulting in more than 20% area reduction compared with standard SRAM solutions, for large memory implementations.