Abstract
Gain-cell embedded DRAM (GC-eDRAM) is a dense, low power option for embedded memory implementation, supporting low supply voltages; however, it suffers from limited data retention time (DRT) and requires periodic refresh operations, limiting its use only to applications that can tolerate temporary memory blockages. In this work we propose a memory architecture based on a novel refreshing algorithm that provides 100% memory availability for the user, resulting in no performance loss for any possible access pattern. This approach allows the memory to have a standard SRAM interface ('vanilla interface'), supporting direct replacement of the SRAM memory with a GC-eDRAM memory. The algorithm/architecture was implemented in a 65 nm CMOS technology resulting in more than 20% area reduction compared with standard SRAM solutions, for large memory implementations.
Original language | English |
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Article number | 9495814 |
Pages (from-to) | 105831-105840 |
Number of pages | 10 |
Journal | IEEE Access |
Volume | 9 |
DOIs | |
State | Published - 2021 |
Keywords
- GC-eDRAM
- Low power
- embedded memory
- gain cells
- hidden refresh
- logic-compatible eDRAM
- retention time
All Science Journal Classification (ASJC) codes
- General Engineering
- General Computer Science
- General Materials Science