TY - GEN
T1 - Realization of Memristor Ratioed Logic with HfO2-Based Resistive RAM
AU - Neuner, Thomas
AU - Kvatinsky, Shahar
N1 - Publisher Copyright: © 2024 IEEE.
PY - 2024
Y1 - 2024
N2 - Emerging nonvolatile memristive memory technologies, such as resistive RAM, offer the potential to perform logic gate operations. One prominent technique is Memristor Ratioed Logic (MRL), which belongs to the non-stateful CMOS counterpart logic group. MRL can execute AND and OR functions using two memristors as voltage dividers. Since both input and output instances are represented as voltages, MRL gates can be seamlessly integrated with CMOS logic, allowing for the construction of complete logic circuits using CMOS inverters. This paper experimentally demonstrates MRL gates based on Hf02 memristors within a crossbar array. We validate the functionality of these gates and identify their limitations, including the nonlinearity, the lack of signal restoration, and certain reliability issues. Additionally, we introduce a memristor initialization mechanism that simplifies the switching process, enhancing the overall performance and reliability of MRL gates.
AB - Emerging nonvolatile memristive memory technologies, such as resistive RAM, offer the potential to perform logic gate operations. One prominent technique is Memristor Ratioed Logic (MRL), which belongs to the non-stateful CMOS counterpart logic group. MRL can execute AND and OR functions using two memristors as voltage dividers. Since both input and output instances are represented as voltages, MRL gates can be seamlessly integrated with CMOS logic, allowing for the construction of complete logic circuits using CMOS inverters. This paper experimentally demonstrates MRL gates based on Hf02 memristors within a crossbar array. We validate the functionality of these gates and identify their limitations, including the nonlinearity, the lack of signal restoration, and certain reliability issues. Additionally, we introduce a memristor initialization mechanism that simplifies the switching process, enhancing the overall performance and reliability of MRL gates.
KW - memristor
KW - memristor-ratioed logic (MRL)
KW - non-statefullogic
KW - reliability
KW - valence change memory (VCM)
UR - https://www.scopus.com/pages/publications/85217617244
U2 - 10.1109/ICECS61496.2024.10848781
DO - 10.1109/ICECS61496.2024.10848781
M3 - منشور من مؤتمر
T3 - Proceedings of the IEEE International Conference on Electronics, Circuits, and Systems
BT - 2024 31st IEEE International Conference on Electronics, Circuits and Systems, ICECS 2024
T2 - 31st IEEE International Conference on Electronics, Circuits and Systems, ICECS 2024
Y2 - 18 November 2024 through 20 November 2024
ER -