TY - GEN
T1 - Promising 2.0
T2 - 41st ACM SIGPLAN Conference on Programming Language Design and Implementation, PLDI 2020
AU - Lee, Sung Hwan
AU - Cho, Minki
AU - Podkopaev, Anton
AU - Chakraborty, Soham
AU - Hur, Chung Kil
AU - Lahav, Ori
AU - Vafeiadis, Viktor
N1 - Publisher Copyright: © 2020 ACM.
PY - 2020/6/11
Y1 - 2020/6/11
N2 - For more than fifteen years, researchers have tried to support global optimizations in a usable semantics for a concurrent programming language, yet this task has been proven to be very difficult because of (1) the infamous "out of thin air" problem, and (2) the subtle interaction between global and thread-local optimizations. In this paper, we present a solution to this problem by redesigning a key component of the promising semantics (PS) of Kang et al. Our updated PS 2.0 model supports all the results known about the original PS model (i.e., thread-local optimizations, hardware mappings, DRF theorems), but additionally enables transformations based on global value-range analysis as well as register promotion (i.e., making accesses to a shared location local if the location is accessed by only one thread). PS 2.0 also resolves a problem with the compilation of relaxed RMWs to ARMv8, which required an unintended extra fence.
AB - For more than fifteen years, researchers have tried to support global optimizations in a usable semantics for a concurrent programming language, yet this task has been proven to be very difficult because of (1) the infamous "out of thin air" problem, and (2) the subtle interaction between global and thread-local optimizations. In this paper, we present a solution to this problem by redesigning a key component of the promising semantics (PS) of Kang et al. Our updated PS 2.0 model supports all the results known about the original PS model (i.e., thread-local optimizations, hardware mappings, DRF theorems), but additionally enables transformations based on global value-range analysis as well as register promotion (i.e., making accesses to a shared location local if the location is accessed by only one thread). PS 2.0 also resolves a problem with the compilation of relaxed RMWs to ARMv8, which required an unintended extra fence.
KW - Compiler Optimizations
KW - Operational Semantics
KW - Relaxed Memory Concurrency
UR - http://www.scopus.com/inward/record.url?scp=85086824529&partnerID=8YFLogxK
U2 - https://doi.org/10.1145/3385412.3386010
DO - https://doi.org/10.1145/3385412.3386010
M3 - منشور من مؤتمر
T3 - Proceedings of the ACM SIGPLAN Conference on Programming Language Design and Implementation (PLDI)
SP - 362
EP - 376
BT - PLDI 2020 - Proceedings of the 41st ACM SIGPLAN Conference on Programming Language Design and Implementation
A2 - Donaldson, Alastair F.
A2 - Torlak, Emina
Y2 - 15 June 2020 through 20 June 2020
ER -