Power-Aware Analog to Digital Converters

Analog to digital converters (ADCs) enable the acquisition of analog signals by representing them in a digital format. Although the architectures and parameters of the ADCs vary with applications, a critical requirement is to keep their power consumption as low as possible. A low-power ADC is very crucial in application areas such as designing mobile and held-held devices that operate on battery power. In this chapter, we focus on three emerging methods that aim at reducing power consumption in the ADCs and have been recently drawing attention in the sampling theory literature. First, we discuss asynchronous time-encoding machines which are an alternative to conventional, clock-based uniform samplers. Such samplers measure time instants at which the integral of a signal crosses a certain threshold. These devices do not require a clock and hence are power efficient. Next, we discuss high-dynamic-range ADCs. Generally, the dynamic range of an ADC should be much greater than that of the signal; otherwise the signal is clipped. However, high-dynamic-range ADCs also require higher power. By using a modulo operator prior to sampling, high-dynamic-range signals can be sampled and recovered using low-dynamic-range and low-power ADCs. We conclude our discussion with systems in which the goal is not to recover the signal but rather an underlying task or function. In such cases we show that we can reduce the power by reducing the bit rate using an analog combiner prior to sampling.