Power Analysis Resilient SRAM Design Implemented with a 1% Area Overhead Impedance Randomization Unit for Security Applications

Robert Giterman; Maoz Wicentowski; Oron Chertkow; Ilan Sever; Ishai Kehati; Yoav Weizman; Osnat Keren; Alexander Fish

doi:10.1109/ESSCIRC.2019.8902622

Power Analysis Resilient SRAM Design Implemented with a 1% Area Overhead Impedance Randomization Unit for Security Applications

Robert Giterman, Maoz Wicentowski, Oron Chertkow, Ilan Sever, Ishai Kehati, Yoav Weizman, Osnat Keren, Alexander Fish

Bar-Ilan University - The Alexander Kofkin Faculty of Engineering

Bar-Ilan University

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

Abstract

Power analysis attacks are an effective tool to extract sensitive information using side-channel analysis,forming a serious threat to IoT systems-on-a-chip (SoCs). Embedded memories implemented with conventional 6T SRAM macrocells often dominate the area and power of these SoCs. In this paper,for the first time,we use silicon measurements to prove that conventional SRAM arrays leak valuable information and that their data can be extracted using power analysis attacks. In order to provide a power analysis resilient embedded memory and adhere to the area constraints of modern SoCs,we implement a low-cost impedance randomization unit,which is integrated into the periphery of a conventional 6T SRAM macro. Preliminary silicon measurements of a 55 nm test-chip implementing the proposed memory array demonstrate a significant information leakage reduction at a low-cost 1% area overhead and no speed and power penalties compared to a conventional SRAM design.

Original language	English
Title of host publication	ESSCIRC 2019 - IEEE 45th European Solid State Circuits Conference
Publisher	Institute of Electrical and Electronics Engineers Inc.
Pages	69-72
Number of pages	4
ISBN (Electronic)	9781728115504
DOIs	https://doi.org/10.1109/ESSCIRC.2019.8902622
State	Published - 1 Sep 2019
Event	45th IEEE European Solid State Circuits Conference, ESSCIRC 2019 - Cracow, Poland Duration: 23 Sep 2019 → 26 Sep 2019

Publication series

Name	ESSCIRC 2019 - IEEE 45th European Solid State Circuits Conference

Conference

Conference	45th IEEE European Solid State Circuits Conference, ESSCIRC 2019
Country/Territory	Poland
City	Cracow
Period	23/09/19 → 26/09/19

All Science Journal Classification (ASJC) codes

Instrumentation
Electronic, Optical and Magnetic Materials
Hardware and Architecture
Electrical and Electronic Engineering

Access to Document

10.1109/ESSCIRC.2019.8902622

Cite this

Giterman, R., Wicentowski, M., Chertkow, O., Sever, I., Kehati, I., Weizman, Y., Keren, O., & Fish, A. (2019). Power Analysis Resilient SRAM Design Implemented with a 1% Area Overhead Impedance Randomization Unit for Security Applications. In ESSCIRC 2019 - IEEE 45th European Solid State Circuits Conference (pp. 69-72). Article 8902622 (ESSCIRC 2019 - IEEE 45th European Solid State Circuits Conference). Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.1109/ESSCIRC.2019.8902622

Giterman, Robert ; Wicentowski, Maoz ; Chertkow, Oron et al. / Power Analysis Resilient SRAM Design Implemented with a 1% Area Overhead Impedance Randomization Unit for Security Applications. ESSCIRC 2019 - IEEE 45th European Solid State Circuits Conference. Institute of Electrical and Electronics Engineers Inc., 2019. pp. 69-72 (ESSCIRC 2019 - IEEE 45th European Solid State Circuits Conference).

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abstract = "Power analysis attacks are an effective tool to extract sensitive information using side-channel analysis,forming a serious threat to IoT systems-on-a-chip (SoCs). Embedded memories implemented with conventional 6T SRAM macrocells often dominate the area and power of these SoCs. In this paper,for the first time,we use silicon measurements to prove that conventional SRAM arrays leak valuable information and that their data can be extracted using power analysis attacks. In order to provide a power analysis resilient embedded memory and adhere to the area constraints of modern SoCs,we implement a low-cost impedance randomization unit,which is integrated into the periphery of a conventional 6T SRAM macro. Preliminary silicon measurements of a 55 nm test-chip implementing the proposed memory array demonstrate a significant information leakage reduction at a low-cost 1% area overhead and no speed and power penalties compared to a conventional SRAM design.",

author = "Robert Giterman and Maoz Wicentowski and Oron Chertkow and Ilan Sever and Ishai Kehati and Yoav Weizman and Osnat Keren and Alexander Fish",

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series = "ESSCIRC 2019 - IEEE 45th European Solid State Circuits Conference",

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Giterman, R, Wicentowski, M, Chertkow, O, Sever, I, Kehati, I, Weizman, Y, Keren, O & Fish, A 2019, Power Analysis Resilient SRAM Design Implemented with a 1% Area Overhead Impedance Randomization Unit for Security Applications. in ESSCIRC 2019 - IEEE 45th European Solid State Circuits Conference., 8902622, ESSCIRC 2019 - IEEE 45th European Solid State Circuits Conference, Institute of Electrical and Electronics Engineers Inc., pp. 69-72, 45th IEEE European Solid State Circuits Conference, ESSCIRC 2019, Cracow, Poland, 23/09/19. https://doi.org/10.1109/ESSCIRC.2019.8902622

Power Analysis Resilient SRAM Design Implemented with a 1% Area Overhead Impedance Randomization Unit for Security Applications. / Giterman, Robert; Wicentowski, Maoz; Chertkow, Oron et al.
ESSCIRC 2019 - IEEE 45th European Solid State Circuits Conference. Institute of Electrical and Electronics Engineers Inc., 2019. p. 69-72 8902622 (ESSCIRC 2019 - IEEE 45th European Solid State Circuits Conference).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

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AU - Giterman, Robert

AU - Wicentowski, Maoz

AU - Chertkow, Oron

AU - Sever, Ilan

AU - Kehati, Ishai

AU - Weizman, Yoav

AU - Keren, Osnat

AU - Fish, Alexander

PY - 2019/9/1

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N2 - Power analysis attacks are an effective tool to extract sensitive information using side-channel analysis,forming a serious threat to IoT systems-on-a-chip (SoCs). Embedded memories implemented with conventional 6T SRAM macrocells often dominate the area and power of these SoCs. In this paper,for the first time,we use silicon measurements to prove that conventional SRAM arrays leak valuable information and that their data can be extracted using power analysis attacks. In order to provide a power analysis resilient embedded memory and adhere to the area constraints of modern SoCs,we implement a low-cost impedance randomization unit,which is integrated into the periphery of a conventional 6T SRAM macro. Preliminary silicon measurements of a 55 nm test-chip implementing the proposed memory array demonstrate a significant information leakage reduction at a low-cost 1% area overhead and no speed and power penalties compared to a conventional SRAM design.

AB - Power analysis attacks are an effective tool to extract sensitive information using side-channel analysis,forming a serious threat to IoT systems-on-a-chip (SoCs). Embedded memories implemented with conventional 6T SRAM macrocells often dominate the area and power of these SoCs. In this paper,for the first time,we use silicon measurements to prove that conventional SRAM arrays leak valuable information and that their data can be extracted using power analysis attacks. In order to provide a power analysis resilient embedded memory and adhere to the area constraints of modern SoCs,we implement a low-cost impedance randomization unit,which is integrated into the periphery of a conventional 6T SRAM macro. Preliminary silicon measurements of a 55 nm test-chip implementing the proposed memory array demonstrate a significant information leakage reduction at a low-cost 1% area overhead and no speed and power penalties compared to a conventional SRAM design.

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M3 - منشور من مؤتمر

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BT - ESSCIRC 2019 - IEEE 45th European Solid State Circuits Conference

PB - Institute of Electrical and Electronics Engineers Inc.

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ER -

Giterman R, Wicentowski M, Chertkow O, Sever I, Kehati I, Weizman Y et al. Power Analysis Resilient SRAM Design Implemented with a 1% Area Overhead Impedance Randomization Unit for Security Applications. In ESSCIRC 2019 - IEEE 45th European Solid State Circuits Conference. Institute of Electrical and Electronics Engineers Inc. 2019. p. 69-72. 8902622. (ESSCIRC 2019 - IEEE 45th European Solid State Circuits Conference). doi: 10.1109/ESSCIRC.2019.8902622

Power Analysis Resilient SRAM Design Implemented with a 1% Area Overhead Impedance Randomization Unit for Security Applications

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