Abstract
We demonstrate a low voltage nonvolatile memory field effect transistor comprising thermal SiO2 tunneling and HfO2 blocking layers as the gate dielectric stack and Au nanocrystals as charge storage nodes. The structure exhibits a memory window of ∼2 V at an applied sweeping voltage of ±3 V which increases to 12.6 at ±12 V. Retention tests show an extrapolated loss of 16% after ten years in the hysteresis width of the threshold voltage. Dynamic program/erase operation reveal an approximately pulse width independent memory for pulse durations of 1 μs to 10 ms; longer pulses increase the memory window while for pulses shorter than 1 μs, the memory windows vanishes. The effective oxide thickness is below 10 nm with very low gate and drain leakage currents.
| Original language | English |
|---|---|
| Article number | 212902 |
| Journal | Applied Physics Letters |
| Volume | 98 |
| Issue number | 21 |
| DOIs | |
| State | Published - 23 May 2011 |
All Science Journal Classification (ASJC) codes
- Physics and Astronomy (miscellaneous)
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