Multipliers-Driven Perturbation of Coefficients for Low-Power Operation in Reconfigurable FIR Filters

Andrea Bonetti, Adam Teman, Philippe Flatresse, Andreas Burg

Research output: Contribution to journalArticlepeer-review

Abstract

Reconfigurable finite-impulse response (FIR) filters are one of the most widely implemented components in Internet of Things systems that require flexibility to support several target applications while consuming the minimum amount of power to comply with the strict design requirements of portable devices. Due to the significant power consumption in the multiplier components of the FIR filter, various techniques aimed at reducing the switching activity of these multipliers have been proposed in the literature. However, these techniques rarely exploit the flexibility on the algorithmic level, which can lead to additional benefits. In this paper, FIR filter multipliers are extensively characterized with power simulations, providing a methodology for the perturbation of the coefficients of baseline filters at the algorithm level to trade-off reduced power consumption for filter quality. The proposed optimization technique does not require any hardware overhead and it enables the possibility of scaling the power consumption of the filter at runtime, while ensuring the full baseline performance of any programmed filter whenever it is required. The analyzed FIR filters were fabricated in a 28nm FD-SOI test chip and measured at a near-threshold, 600mV supply voltage. For example, by carefully choosing slightly perturbed coefficients in a low-pass configuration, power savings of up to 33% are achieved when accepting a 3dB degradation on the stopband, as compared with the baseline implementation of the filter.

Original languageEnglish
Article number7927747
Pages (from-to)2388-2400
Number of pages13
JournalIEEE Transactions on Circuits and Systems I: Regular Papers
Volume64
Issue number9
DOIs
StatePublished - Sep 2017

Keywords

  • FIR filters
  • VLSI signal processing
  • approximate computing
  • digital multipliers
  • low-power design

All Science Journal Classification (ASJC) codes

  • Electrical and Electronic Engineering
  • Hardware and Architecture

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