MRL - Memristor Ratioed Logic

Shahar Kvatinsky, Nimrod Wald, Guy Satat, Avinoam Kolodny, Uri C. Weiser, Eby G. Friedman

Research output: Chapter in Book/Report/Conference proceedingConference contributionpeer-review

Abstract

Memristive devices are novel structures, developed primarily as memory. Another interesting application for memristive devices is logic circuits. In this paper, MRL (Memristor Ratioed Logic) - a hybrid CMOS-memristive logic family - is described. In this logic family, OR and AND logic gates are based on memristive devices, and CMOS inverters are added to provide a complete logic structure and signal restoration. Unlike previously published memristive-based logic families, the MRL family is compatible with standard CMOS logic. A case study of an eight-bit full adder is presented and related design considerations are discussed.

Original languageEnglish
Title of host publication2012 13th International Workshop on Cellular Nanoscale Networks and their Applications, CNNA 2012
DOIs
StatePublished - 2012
Event2012 13th International Workshop on Cellular Nanoscale Networks and their Applications, CNNA 2012 - Turin, Italy
Duration: 29 Aug 201229 Aug 2012

Conference

Conference2012 13th International Workshop on Cellular Nanoscale Networks and their Applications, CNNA 2012
Country/TerritoryItaly
CityTurin
Period29/08/1229/08/12

All Science Journal Classification (ASJC) codes

  • Computer Networks and Communications
  • Electrical and Electronic Engineering

Fingerprint

Dive into the research topics of 'MRL - Memristor Ratioed Logic'. Together they form a unique fingerprint.

Cite this