Minimizing delay in shared pipelines

Ori Rottenstreich, Isaac Keslassy, Yoram Revah, Aviran Kadosh

Research output: Chapter in Book/Report/Conference proceedingConference contributionpeer-review

Abstract

Pipelines are widely used to increase throughput in multi-core chips by parallelizing packet processing. Typically, each packet type is serviced by a dedicated pipeline. However, with the increase in the number of packet types and their number of required services, there are not enough cores for pipelines. In this paper, we study pipeline sharing, such that a single pipeline can be used to serve several packet types. Pipeline sharing decreases the needed total number of cores, but typically increases pipeline lengths and therefore packet delays. We consider the optimization problem of allocating cores between different packet types such that the average delay is minimized. We suggest a polynomial-time algorithm that finds the optimal solution when the packet types preserve a specific property. We also present a greedy algorithm for the general case. Last, we examine our solutions on synthetic examples, on packet-processing applications, and on real-life H.264 standard requirements.

Original languageEnglish
Title of host publicationProceedings - IEEE 21st Annual Symposium on High-Performance Interconnects, HOTI 2013
Pages9-16
Number of pages8
DOIs
StatePublished - 1 Jan 2013
Event21st IEEE Annual Symposium on High-Performance Interconnects, HOTI 2013 - San Jose, CA, United States
Duration: 21 Aug 201323 Aug 2013

Publication series

NameProceedings - IEEE 21st Annual Symposium on High-Performance Interconnects, HOTI 2013

Conference

Conference21st IEEE Annual Symposium on High-Performance Interconnects, HOTI 2013
Country/TerritoryUnited States
CitySan Jose, CA
Period21/08/1323/08/13

Keywords

  • Delay
  • Multi-core chip
  • Shared Pipelines

All Science Journal Classification (ASJC) codes

  • Electrical and Electronic Engineering

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