Introduction to Dual Mode Logic (DML)

Itamar Levi; Alexander Fish

doi:10.1007/978-3-030-40786-5_2

Introduction to Dual Mode Logic (DML)

Research output: Chapter in Book/Report/Conference proceeding › Chapter

Abstract

This chapter discusses the concept behind DML. It presents DML basic architectures at the circuit level and describes the two modes of DML operation in detail. Specifically, it elaborates on the range of device-level topologies to construct a DML gate and the valid...

Original language	English GB
Title of host publication	Dual Mode Logic
Place of Publication	Cham, Switzerland
Pages	25-33
Number of pages	9
DOIs	https://doi.org/10.1007/978-3-030-40786-5_2
State	Published - 16 Dec 2020

Keywords

Critical path (CP)
Drive strength
Dual mode logic (DML)
Dynamic mode
Keeper
Minimum delay point (MDP)
Minimum energy point (MEP)
Pull-down network (PDN)
Pull-up network (PUN)
Sizing
Static logic
Static mode
Type-A
Type-B
Un-footed
Upsizing

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10.1007/978-3-030-40786-5_2

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KW - Dynamic mode

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KW - Minimum delay point (MDP)

KW - Minimum energy point (MEP)

KW - Pull-down network (PDN)

KW - Pull-up network (PUN)

KW - Sizing

KW - Static logic

KW - Static mode

KW - Type-A

KW - Type-B

KW - Un-footed

KW - Upsizing

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CY - Cham, Switzerland

ER -

Introduction to Dual Mode Logic (DML)

Abstract

Keywords

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