Introduction to Dual Mode Logic (DML)

Itamar Levi; Alexander Fish

doi:https://doi.org/10.1007/978-3-030-40786-5_2

Introduction to Dual Mode Logic (DML)

Itamar Levi, Alexander Fish

Bar-Ilan University - The Alexander Kofkin Faculty of Engineering

Bar-Ilan University

Research output: Chapter in Book/Report/Conference proceeding › Chapter

Abstract

This chapter discusses the concept behind DML. It presents DML basic architectures at the circuit level and describes the two modes of DML operation in detail. Specifically, it elaborates on the range of device-level topologies to construct a DML gate and the valid...

Original language	English
Title of host publication	Dual Mode Logic
Place of Publication	Cham, Switzerland
Pages	25-33
Number of pages	9
DOIs	https://doi.org/10.1007/978-3-030-40786-5_2
State	Published - 16 Dec 2020

Keywords

Critical path (CP)
Drive strength
Dual mode logic (DML)
Dynamic mode
Keeper
Minimum delay point (MDP)
Minimum energy point (MEP)
Pull-down network (PDN)
Pull-up network (PUN)
Sizing
Static logic
Static mode
Type-A
Type-B
Un-footed
Upsizing

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https://doi.org/10.1007/978-3-030-40786-5_2

Cite this

@inbook{eb2ec5d1efe44f00846290c3c33d2799,

title = "Introduction to Dual Mode Logic (DML)",

abstract = "This chapter discusses the concept behind DML. It presents DML basic architectures at the circuit level and describes the two modes of DML operation in detail. Specifically, it elaborates on the range of device-level topologies to construct a DML gate and the valid...",

keywords = "Critical path (CP), Drive strength, Dual mode logic (DML), Dynamic mode, Keeper, Minimum delay point (MDP), Minimum energy point (MEP), Pull-down network (PDN), Pull-up network (PUN), Sizing, Static logic, Static mode, Type-A, Type-B, Un-footed, Upsizing",

author = "Itamar Levi and Alexander Fish",

year = "2020",

month = dec,

day = "16",

doi = "https://doi.org/10.1007/978-3-030-40786-5_2",

language = "الإنجليزيّة",

pages = "25--33",

booktitle = "Dual Mode Logic",

}

TY - CHAP

T1 - Introduction to Dual Mode Logic (DML)

AU - Levi, Itamar

AU - Fish, Alexander

PY - 2020/12/16

Y1 - 2020/12/16

N2 - This chapter discusses the concept behind DML. It presents DML basic architectures at the circuit level and describes the two modes of DML operation in detail. Specifically, it elaborates on the range of device-level topologies to construct a DML gate and the valid...

AB - This chapter discusses the concept behind DML. It presents DML basic architectures at the circuit level and describes the two modes of DML operation in detail. Specifically, it elaborates on the range of device-level topologies to construct a DML gate and the valid...

KW - Critical path (CP)

KW - Drive strength

KW - Dual mode logic (DML)

KW - Dynamic mode

KW - Keeper

KW - Minimum delay point (MDP)

KW - Minimum energy point (MEP)

KW - Pull-down network (PDN)

KW - Pull-up network (PUN)

KW - Sizing

KW - Static logic

KW - Static mode

KW - Type-A

KW - Type-B

KW - Un-footed

KW - Upsizing

UR - https://www.mendeley.com/catalogue/b46a239d-bc73-387c-86c7-8df2aa69dbd1/

U2 - https://doi.org/10.1007/978-3-030-40786-5_2

DO - https://doi.org/10.1007/978-3-030-40786-5_2

M3 - فصل

SP - 25

EP - 33

BT - Dual Mode Logic

CY - Cham, Switzerland

ER -

Introduction to Dual Mode Logic (DML)

Abstract

Keywords

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