TY - JOUR
T1 - IMAGING
T2 - In-Memory AlGorithms for Image processiNG
AU - Haj-Ali, Ameer
AU - Ben-Hur, Rotem
AU - Wald, Nimrod
AU - Ronen, Ronny
AU - Kvatinsky, Shahar
N1 - Funding Information: Manuscript received March 3, 2018; revised April 22, 2018, May 18, 2018, and June 4, 2018; accepted June 5, 2018. Date of publication June 27, 2018; date of current version October 23, 2018. This work was supported in part by the European Research Council through the European Union’s Horizon 2020 Research and Innovation Programme under Grant 757259, in part by the Viterbi Fellowship at the Technion Computer Engineering Center, in part by the EU ICT COST Action IC1401, and in part by the Israel Science Foundation under Grant 1514/17. This paper was recommended by Associate Editor D. Comminiello. (Corresponding author: Ameer Haj-Ali.) The authors are with the Andrew and Erna Viterbi Faculty of Electrical Engineering, Technion–Israel Institute of Technology, Haifa 32000, Israel (e-mail: [email protected]; [email protected]; [email protected]; [email protected]; shahar@ee. technion.ac.il). Publisher Copyright: © 2018 IEEE.
PY - 2018/12/1
Y1 - 2018/12/1
N2 - Data-intensive applications such as image processing suffer from massive data movement between memory and processing units. The severe limitations on system performance and energy efficiency imposed by this data movement are further exacerbated with any increase in the distance the data must travel. This data transfer and its associated obstacles could be eliminated by the use of emerging non-volatile resistive memory technologies (memristors) that make it possible to both store and process data within the same memory cells. In this paper, we propose four in-memory algorithms for efficient execution of fixed point multiplication using MAGIC gates. These algorithms achieve much better latency and throughput than a previous work and significantly reduce the area cost. They can thus be feasibly implemented inside the size-limited memory arrays. We use these fixed point multiplication algorithms to efficiently perform more complex in-memory operations such as image convolution and further show how to partition large images to multiple memory arrays so as to maximize the parallelism. All the proposed algorithms are evaluated and verified using a cycle-accurate and functional simulator. Our algorithms provide on average 200 × better performance over state-of-the-art APIM, a processing in-memory architecture for data intensive applications.
AB - Data-intensive applications such as image processing suffer from massive data movement between memory and processing units. The severe limitations on system performance and energy efficiency imposed by this data movement are further exacerbated with any increase in the distance the data must travel. This data transfer and its associated obstacles could be eliminated by the use of emerging non-volatile resistive memory technologies (memristors) that make it possible to both store and process data within the same memory cells. In this paper, we propose four in-memory algorithms for efficient execution of fixed point multiplication using MAGIC gates. These algorithms achieve much better latency and throughput than a previous work and significantly reduce the area cost. They can thus be feasibly implemented inside the size-limited memory arrays. We use these fixed point multiplication algorithms to efficiently perform more complex in-memory operations such as image convolution and further show how to partition large images to multiple memory arrays so as to maximize the parallelism. All the proposed algorithms are evaluated and verified using a cycle-accurate and functional simulator. Our algorithms provide on average 200 × better performance over state-of-the-art APIM, a processing in-memory architecture for data intensive applications.
KW - MAGIC
KW - algorithms
KW - memristors
KW - processing in memory
KW - von Neumann bottleneck
UR - https://www.scopus.com/pages/publications/85049143742
U2 - 10.1109/TCSI.2018.2846699
DO - 10.1109/TCSI.2018.2846699
M3 - Article
SN - 1549-8328
VL - 65
SP - 4258
EP - 4271
JO - IEEE Transactions on Circuits and Systems I: Regular Papers
JF - IEEE Transactions on Circuits and Systems I: Regular Papers
IS - 12
M1 - 8398398
ER -