TY - GEN
T1 - High Density GC-eDRAM Design in 16nm FinFET
AU - Shalom, Amir
AU - Giterman, Robert
AU - Teman, Adam
N1 - Publisher Copyright: © 2018 IEEE.
PY - 2018/7/2
Y1 - 2018/7/2
N2 - Gain-cell embedded DRAM (GC-eDRAM) is an interesting alternative to conventional six-transistor (6T) static random access memory (SRAM) cells, offering higher density, lower leakage, and two-ported operation. However, process scaling and the migration to FinFET technologies have brought new challenges to the design of GC-eDRAM cells, including significant changes in device leakage characteristics, resulting in reduced data retention times (DRTs) and new layout rules, affecting the area benefits of known GC-eDRAM topologies. In this paper, for the first time, we examine different GC-eDRAM topologies in a foundry-based 16 nm FinFET technology. Based on this analysis, we develop a methodology for the best practice design of GC-eDRAM in FinFET technologies, based on the transistor characteristics and layout constraints. The developed methodology demonstrates the potential benefits of GC-eDRAM in 16 nm FinFET technology and beyond.
AB - Gain-cell embedded DRAM (GC-eDRAM) is an interesting alternative to conventional six-transistor (6T) static random access memory (SRAM) cells, offering higher density, lower leakage, and two-ported operation. However, process scaling and the migration to FinFET technologies have brought new challenges to the design of GC-eDRAM cells, including significant changes in device leakage characteristics, resulting in reduced data retention times (DRTs) and new layout rules, affecting the area benefits of known GC-eDRAM topologies. In this paper, for the first time, we examine different GC-eDRAM topologies in a foundry-based 16 nm FinFET technology. Based on this analysis, we develop a methodology for the best practice design of GC-eDRAM in FinFET technologies, based on the transistor characteristics and layout constraints. The developed methodology demonstrates the potential benefits of GC-eDRAM in 16 nm FinFET technology and beyond.
UR - http://www.scopus.com/inward/record.url?scp=85062295032&partnerID=8YFLogxK
U2 - https://doi.org/10.1109/ICECS.2018.8618019
DO - https://doi.org/10.1109/ICECS.2018.8618019
M3 - منشور من مؤتمر
T3 - 2018 25th IEEE International Conference on Electronics Circuits and Systems, ICECS 2018
SP - 585
EP - 588
BT - 2018 25th IEEE International Conference on Electronics Circuits and Systems, ICECS 2018
PB - Institute of Electrical and Electronics Engineers Inc.
T2 - 25th IEEE International Conference on Electronics Circuits and Systems, ICECS 2018
Y2 - 9 December 2018 through 12 December 2018
ER -