@inproceedings{325a9bcc28f24c85ba0a79b577d32762,
title = "FPGA implementation of pAsynch design paradigm",
abstract = "Information leakage through physical channels is a major security vulnerability for embedded hardware. Power analysis is a well known technique used for side channel attacks. This paper overviews a new design paradigm, dubbed pAsynch, recently proposed by our group as an effective circuit level countermeasure against Power Analysis Attacks. pAsynch utilizes both the internal state and random signals to uniformly spread the information-carrying energy within the clock period. This paper is based on previous publications discussing pAsynch in detail and focuses on the practical implementation of pAsynch protection scheme on FPGA, overcoming some of the inherent challenges associated with the clocking scheme that is the basis of this technique. We show that pAsynch can provide h/w security with low overhead, making it suitable for energy/area constrained applications.",
keywords = "FPGA, Hardware security, Information leakage, PAsynch, Pseudo asynchronous, Side channel",
author = "Yehuda Rudin and Itamar Levi and Alexander Fish and Osnat Keren",
note = "Publisher Copyright: {\textcopyright} 2019 IEEE.; 10th IFIP International Conference on New Technologies, Mobility and Security, NTMS 2019 ; Conference date: 24-06-2019 Through 26-06-2019",
year = "2019",
month = jun,
day = "1",
doi = "https://doi.org/10.1109/NTMS.2019.8763813",
language = "الإنجليزيّة",
series = "2019 10th IFIP International Conference on New Technologies, Mobility and Security, NTMS 2019 - Proceedings and Workshop",
publisher = "Institute of Electrical and Electronics Engineers Inc.",
booktitle = "2019 10th IFIP International Conference on New Technologies, Mobility and Security, NTMS 2019 - Proceedings and Workshop",
address = "الولايات المتّحدة",
}