TY - GEN
T1 - FlexDriver
T2 - 27th ACM International Conference on Architectural Support for Programming Languages and Operating Systems, ASPLOS 2022
AU - Eran, Haggai
AU - Fudim, Maxim
AU - Malka, Gabi
AU - Shalom, Gal
AU - Cohen, Noam
AU - Hermony, Amit
AU - Levi, Dotan
AU - Liss, Liran
AU - Silberstein, Mark
N1 - Publisher Copyright: © 2022 ACM.
PY - 2022/2/28
Y1 - 2022/2/28
N2 - We propose a new system design for connecting hardware and FPGA accelerators to the network, allowing the accelerator to directly control commodity Network Interface Cards (NICs) without using the CPU. This enables us to solve the key challenge of leveraging existing NIC hardware offloads such as virtualization, tunneling, and RDMA for accelerator networking. Our approach supports a diverse set of use cases, from direct network access for disaggregated accelerators to inline-Acceleration of the network stack, all without the complex networking logic in the accelerator. To demonstrate the feasibility of this approach, we build FlexDriver (FLD), an on-Accelerator hardware module that implements a NIC data-plane driver. Our main technical contribution is a mechanism that compresses the NIC control structures by two orders of magnitude, allowing FLD to achieve high networking scalability with low die area cost and no bandwidth interference with the accelerator logic. The prototype for NVIDIA Innova-2 FPGA SmartNICs showcases our design's utility for three different accelerators: A disaggregated LTE cipher, an IP-defragmentation inline accelerator, and an IoT cryptographic-Token authentication offload. These accelerators reach 25 Gbps line rate and leverage the NIC for RDMA processing, VXLAN tunneling, and traffic shaping without CPU involvement.
AB - We propose a new system design for connecting hardware and FPGA accelerators to the network, allowing the accelerator to directly control commodity Network Interface Cards (NICs) without using the CPU. This enables us to solve the key challenge of leveraging existing NIC hardware offloads such as virtualization, tunneling, and RDMA for accelerator networking. Our approach supports a diverse set of use cases, from direct network access for disaggregated accelerators to inline-Acceleration of the network stack, all without the complex networking logic in the accelerator. To demonstrate the feasibility of this approach, we build FlexDriver (FLD), an on-Accelerator hardware module that implements a NIC data-plane driver. Our main technical contribution is a mechanism that compresses the NIC control structures by two orders of magnitude, allowing FLD to achieve high networking scalability with low die area cost and no bandwidth interference with the accelerator logic. The prototype for NVIDIA Innova-2 FPGA SmartNICs showcases our design's utility for three different accelerators: A disaggregated LTE cipher, an IP-defragmentation inline accelerator, and an IoT cryptographic-Token authentication offload. These accelerators reach 25 Gbps line rate and leverage the NIC for RDMA processing, VXLAN tunneling, and traffic shaping without CPU involvement.
KW - accelerator disaggregation
KW - accelerator networking
KW - network function acceleration
UR - http://www.scopus.com/inward/record.url?scp=85126393876&partnerID=8YFLogxK
U2 - 10.1145/3503222.3507776
DO - 10.1145/3503222.3507776
M3 - منشور من مؤتمر
T3 - International Conference on Architectural Support for Programming Languages and Operating Systems - ASPLOS
SP - 1115
EP - 1129
BT - ASPLOS 2022 - Proceedings of the 27th ACM International Conference on Architectural Support for Programming Languages and Operating Systems
A2 - Falsafi, Babak
A2 - Ferdman, Michael
A2 - Lu, Shan
A2 - Wenisch, Thomas F.
Y2 - 28 February 2022 through 4 March 2022
ER -