@inproceedings{42abd77c9e1f40a5a02682da65f9b241,
title = "First order temporal logic monitoring with BDDs",
abstract = "Runtime verification is aimed at analyzing execution traces stemming from a running program or system. The traditional purpose is to detect the lack of conformance with respect to a formal specification. Numerous efforts in the field have focused on monitoring so-called parametric specifications, where events carry data, and formulas can refer to such. Since a monitor for such specifications has to store observed data, the challenge is to have an efficient representation and manipulation of Boolean operators, quantification, and lookup of data. The fundamental problem is that the actual values of the data are not necessarily bounded or provided in advance. In this work we explore the use of Binary Decision Diagrams (BDDs) for representing observed data. Our experiments show a substantial improvement in performance compared to related work.",
author = "Klaus Havelund and Doron Peled and Dogan Ulus",
note = "Publisher Copyright: {\textcopyright} 2017 FMCAD Inc.; 17th Conference on Formal Methods in Computer-Aided Design, FMCAD 2017 ; Conference date: 02-10-2017 Through 06-10-2017",
year = "2017",
month = nov,
day = "8",
doi = "10.23919/fmcad.2017.8102249",
language = "الإنجليزيّة",
series = "Proceedings of the 17th Conference on Formal Methods in Computer-Aided Design, FMCAD 2017",
publisher = "Institute of Electrical and Electronics Engineers Inc.",
pages = "116--123",
editor = "Georg Weissenbacher and Daryl Stewart",
booktitle = "Proceedings of the 17th Conference on Formal Methods in Computer-Aided Design, FMCAD 2017",
address = "الولايات المتّحدة",
}