Experimental Demonstration of Non-Stateful In-Memory Logic With 1T1R OxRAM Valence Change Mechanism Memristors

Henriette Padberg, Amir Regev, Giuseppe Piccolboni, Alessandro Bricalli, Gabriel Molas, Jean Francois Nodin, Shahar Kvatinsky

Research output: Contribution to journalArticlepeer-review

Abstract

Processing-in-memory (PIM) is attractive to overcome the limitations of modern computing systems. Numerous PIM systems exist, varying by the technologies and logic techniques used. Successful operation of specific logic functions is crucial for effective processing-in-memory. Memristive non-stateful logic techniques are compatible with CMOS logic and can be integrated into a 1T1R memory array, similar to commercial RRAM products. This brief analyzes and demonstrates two non-stateful logic techniques: 1T1R logic and scouting logic. As a first step, the used 1T1R SiOx valence change mechanism memristors are characterized in reference to their feasibility to perform logic functions. Various logical functions of the two logic techniques are experimentally demonstrated, showing correct functionality in all cases. Following the results, the challenges and limitations of the RRAM characteristics and 1T1R configuration for the application in logical functions are discussed.

Original languageEnglish
Pages (from-to)395-399
Number of pages5
JournalIEEE Transactions on Circuits and Systems II: Express Briefs
Volume71
Issue number1
DOIs
StatePublished - 1 Jan 2024

Keywords

  • 1T1R Logic
  • Current measurement
  • Experimental Demonstration
  • Logic arrays
  • Logic gates
  • Memristors
  • Non-Stateful Logic
  • Reliability Issues
  • Resistance
  • Scouting Logic
  • Switches
  • Transistors

All Science Journal Classification (ASJC) codes

  • Electrical and Electronic Engineering

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