Enhanced Performance Fully-Synthesizable ΣΔ ADC for Efficient Digital Voltage-Mode Control

This paper introduces a new approach for sigma-delta based analog to digital converter (SDADC) with enhanced performance suitable for digital voltage regulation. The new ADC increases the number of digital representations of the sampled signal per conversion cycle, for the same oversampling clock frequency. This advantage also translates to reduced power consumption for the same conversion rate since slower clock can be employed to obtain similar conversion rate. An all-digital, fully-synthesizable realization of the new architecture sets it as an attractive candidate for many digital application platforms, ranging from housekeeping and monitoring, and even as the primary ADC for the compensation loop. High accuracy and fast effective conversion rate have been verified through simulation and experiments, demonstrating wide range of sampled voltages with less than 1% error for wide operation range. An experimental closed-loop operation on a voltage-mode (VM) buck converter, with the digital voltage loop implemented on FPGA, demonstrates superior operation over a conventional SD operation. The digital controller core including the new SDADC have been also implemented as IC by an automated synthesis process and place- and route tools in a 0.18μ m 5V CMOS process resulting in effective silicon area of 0.07mm².