@inproceedings{5b57043ebd644ba398d41118c1605eb1,
title = "Energy-delay tradeoffs of low-voltage dual mode logic in 28nm FD-SOI",
abstract = "In this paper, the Dual Mode Logic (DML) technique is evaluated on a low-voltage 16-bit Carry Skip Adder in 28 nm UTBB FD-SOI technology. By combining the operating characteristics of the DML and the unique features of the technology, energy/speed efficient low-voltage adder designs can be defined. More precisely, it is demonstrated that, the capability of the DML design to switch on-the-fly between static and dynamic modes of operation leads to an improvement of more than 20% in terms of energy-delay product (EDP) in comparison to the conventional CMOS design. Moreover, the high efficiency of back plane biasing in the adopted technology allows very fine tuning of energy-delay performances of a DML design, thus emphasizing its intrinsic versatility.",
keywords = "Dual mode logic (DML), carry skip adder, low-voltage",
author = "Ramiro Taco and Itamar Levi and Marco Lanuzza and Alexander Fish",
note = "Publisher Copyright: {\textcopyright} 2017 IEEE.; 2017 IEEE SOI-3D-Subthreshold Microelectronics Unified Conference, S3S 2017 ; Conference date: 16-10-2017 Through 18-10-2017",
year = "2017",
month = jul,
day = "2",
doi = "https://doi.org/10.1109/s3s.2017.8309250",
language = "الإنجليزيّة",
series = "2017 IEEE SOI-3D-Subthreshold Microelectronics Unified Conference, S3S 2017",
publisher = "Institute of Electrical and Electronics Engineers Inc.",
pages = "1--3",
booktitle = "2017 IEEE SOI-3D-Subthreshold Microelectronics Unified Conference, S3S 2017",
address = "الولايات المتّحدة",
}