Dual-Mode Low-Drop-Out Regulator/Power Gate With Linear and On-Off Conduction for Microprocessor Core On-Die Supply Voltages in 14 nm

Kosta Luria; Joseph Shor; Michael Zelikson; Alex Lyakhov

doi:10.1109/jssc.2015.2512387

Dual-Mode Low-Drop-Out Regulator/Power Gate With Linear and On-Off Conduction for Microprocessor Core On-Die Supply Voltages in 14 nm

Kosta Luria, Joseph Shor, Michael Zelikson, Alex Lyakhov

Bar-Ilan University - The Alexander Kofkin Faculty of Engineering

Bar-Ilan University

Research output: Contribution to journal › Article › peer-review

Abstract

A dual-mode digital power gate (PG) and linear low-drop-out regulator (LDO) has been demonstrated in 14 nm. A modified flipped source follower driver circuit is used to minimize dI/dt droops. The LDO has a novel compensation method which utilizes capacitance multiplication and can drive a 1-7 μF load without any external compensation elements. This LDO exhibits high-current drive capability (3 A) at low-dropout voltages (< 60 mV) and high-current efficiency (> 99%), making it suitable to drive a microprocessor core.

Original language	English
Article number	7383230
Pages (from-to)	752-762
Number of pages	11
Journal	IEEE Journal of Solid-State Circuits
Volume	51
Issue number	3
DOIs	https://doi.org/10.1109/jssc.2015.2512387
State	Published - Mar 2016

Keywords

Analog
low-drop-out regulator (LDO)
microprocessors
power management

All Science Journal Classification (ASJC) codes

Electrical and Electronic Engineering

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10.1109/jssc.2015.2512387

Cite this

@article{a63563c98f044827a40a83a365766570,

title = "Dual-Mode Low-Drop-Out Regulator/Power Gate With Linear and On-Off Conduction for Microprocessor Core On-Die Supply Voltages in 14 nm",

abstract = "A dual-mode digital power gate (PG) and linear low-drop-out regulator (LDO) has been demonstrated in 14 nm. A modified flipped source follower driver circuit is used to minimize dI/dt droops. The LDO has a novel compensation method which utilizes capacitance multiplication and can drive a 1-7 μF load without any external compensation elements. This LDO exhibits high-current drive capability (3 A) at low-dropout voltages (< 60 mV) and high-current efficiency (> 99%), making it suitable to drive a microprocessor core.",

keywords = "Analog, low-drop-out regulator (LDO), microprocessors, power management",

author = "Kosta Luria and Joseph Shor and Michael Zelikson and Alex Lyakhov",

note = "Publisher Copyright: {\textcopyright} 2015 IEEE.",

year = "2016",

month = mar,

doi = "10.1109/jssc.2015.2512387",

language = "الإنجليزيّة",

volume = "51",

pages = "752--762",

journal = "IEEE Journal of Solid-State Circuits",

issn = "0018-9200",

publisher = "Institute of Electrical and Electronics Engineers Inc.",

number = "3",

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T1 - Dual-Mode Low-Drop-Out Regulator/Power Gate With Linear and On-Off Conduction for Microprocessor Core On-Die Supply Voltages in 14 nm

AU - Luria, Kosta

AU - Shor, Joseph

AU - Zelikson, Michael

AU - Lyakhov, Alex

PY - 2016/3

Y1 - 2016/3

N2 - A dual-mode digital power gate (PG) and linear low-drop-out regulator (LDO) has been demonstrated in 14 nm. A modified flipped source follower driver circuit is used to minimize dI/dt droops. The LDO has a novel compensation method which utilizes capacitance multiplication and can drive a 1-7 μF load without any external compensation elements. This LDO exhibits high-current drive capability (3 A) at low-dropout voltages (< 60 mV) and high-current efficiency (> 99%), making it suitable to drive a microprocessor core.

AB - A dual-mode digital power gate (PG) and linear low-drop-out regulator (LDO) has been demonstrated in 14 nm. A modified flipped source follower driver circuit is used to minimize dI/dt droops. The LDO has a novel compensation method which utilizes capacitance multiplication and can drive a 1-7 μF load without any external compensation elements. This LDO exhibits high-current drive capability (3 A) at low-dropout voltages (< 60 mV) and high-current efficiency (> 99%), making it suitable to drive a microprocessor core.

KW - Analog

KW - low-drop-out regulator (LDO)

KW - microprocessors

KW - power management

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U2 - 10.1109/jssc.2015.2512387

DO - 10.1109/jssc.2015.2512387

M3 - مقالة

SN - 0018-9200

VL - 51

SP - 752

EP - 762

JO - IEEE Journal of Solid-State Circuits

JF - IEEE Journal of Solid-State Circuits

IS - 3

M1 - 7383230

ER -

Dual-Mode Low-Drop-Out Regulator/Power Gate With Linear and On-Off Conduction for Microprocessor Core On-Die Supply Voltages in 14 nm

Abstract

Keywords

All Science Journal Classification (ASJC) codes

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