Dual Mode Logic in FD-SOI Technology

Itamar Levi; Alexander Fish

doi:10.1007/978-3-030-40786-5_9

Dual Mode Logic in FD-SOI Technology

Research output: Chapter in Book/Report/Conference proceeding › Chapter

Abstract

Now that we have explored DML operation and efficiency in a conventional bulk CMOS, this chapter evaluates the DML technique in a relatively advanced 28 nm FD-SOI technology. Throughout, we provide fabricated ASIC measurements data to support the analysis and...

Original language	English
Title of host publication	Dual Mode Logic
Place of Publication	Cham, Switzerland
Pages	157-176
Number of pages	20
DOIs	https://doi.org/10.1007/978-3-030-40786-5_9
State	Published - 16 Dec 2020

Keywords

ASIC
Buried oxide (BOX)
CMOS
Carry skip adder (CSA)
DML
Drain-induced barrier lowering (DIBL)
Dynamically adaptable
Forward body bias (FBB)
Full adder (FA)
Fully depleted silicon on insulator (FD-SOI)
High-voltage threshold (HVT)
Low-voltage threshold (LVT)
Multiply-accumulate (MAC)
Near threshold
Partial product reduction tree (PPRT)
Performance
Prediction circuit (PC)
Reverse body bias (RBB)
Robustness
Temperature variation
Ultra-thin body and box (UTBB)
Variability

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10.1007/978-3-030-40786-5_9

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title = "Dual Mode Logic in FD-SOI Technology",

abstract = "Now that we have explored DML operation and efficiency in a conventional bulk CMOS, this chapter evaluates the DML technique in a relatively advanced 28 nm FD-SOI technology. Throughout, we provide fabricated ASIC measurements data to support the analysis and...",

keywords = "ASIC, Buried oxide (BOX), CMOS, Carry skip adder (CSA), DML, Drain-induced barrier lowering (DIBL), Dynamically adaptable, Forward body bias (FBB), Full adder (FA), Fully depleted silicon on insulator (FD-SOI), High-voltage threshold (HVT), Low-voltage threshold (LVT), Multiply-accumulate (MAC), Near threshold, Partial product reduction tree (PPRT), Performance, Prediction circuit (PC), Reverse body bias (RBB), Robustness, Temperature variation, Ultra-thin body and box (UTBB), Variability",

author = "Itamar Levi and Alexander Fish",

year = "2020",

month = dec,

day = "16",

doi = "10.1007/978-3-030-40786-5\_9",

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AU - Fish, Alexander

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Y1 - 2020/12/16

N2 - Now that we have explored DML operation and efficiency in a conventional bulk CMOS, this chapter evaluates the DML technique in a relatively advanced 28 nm FD-SOI technology. Throughout, we provide fabricated ASIC measurements data to support the analysis and...

AB - Now that we have explored DML operation and efficiency in a conventional bulk CMOS, this chapter evaluates the DML technique in a relatively advanced 28 nm FD-SOI technology. Throughout, we provide fabricated ASIC measurements data to support the analysis and...

KW - ASIC

KW - Buried oxide (BOX)

KW - CMOS

KW - Carry skip adder (CSA)

KW - DML

KW - Drain-induced barrier lowering (DIBL)

KW - Dynamically adaptable

KW - Forward body bias (FBB)

KW - Full adder (FA)

KW - Fully depleted silicon on insulator (FD-SOI)

KW - High-voltage threshold (HVT)

KW - Low-voltage threshold (LVT)

KW - Multiply-accumulate (MAC)

KW - Near threshold

KW - Partial product reduction tree (PPRT)

KW - Performance

KW - Prediction circuit (PC)

KW - Reverse body bias (RBB)

KW - Robustness

KW - Temperature variation

KW - Ultra-thin body and box (UTBB)

KW - Variability

UR - https://www.mendeley.com/catalogue/de4cf3f5-8e2e-34ab-a691-dd75d19ba880/

U2 - 10.1007/978-3-030-40786-5_9

DO - 10.1007/978-3-030-40786-5_9

M3 - فصل

SP - 157

EP - 176

BT - Dual Mode Logic

CY - Cham, Switzerland

ER -

Dual Mode Logic in FD-SOI Technology

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Keywords

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