Dual mode logic address decoder

Leonid Yavits; Ramiro Taco; Netanel Shavit; Inbal Stanger; Alexander Fish

Dual mode logic address decoder

Leonid Yavits, Ramiro Taco, Netanel Shavit, Inbal Stanger, Alexander Fish

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

Abstract

Address decoders are integral components of random access memories. In higher-performance computing, the timing of address decoders is often critical, especially in applications such as translation lookaside buffer (TLB) and first level data cache. On the other hand, memory power budget and energy consumption are equally critically important for battery-powered devices. Dual Mode Logic (DML) has been shown to combine the support for both requirements in a single circuit. We present a novel DML based address decoder design and compare it with conventional static CMOS and np-CMOS address decoders. Simulations show that DML based address decoder in dynamic mode achieves 31% lower delay compared to conventional static CMOS implementation. In static mode, DML based address decoder reduces the energy consumption by 29% and reaches 10% lower energy-delay product compared to static CMOS address decoder. This is the first time DML is evaluated in 16nm FinFet process.

Original language	American English
Title of host publication	2020 IEEE International Symposium on Circuits and Systems, ISCAS 2020 - Proceedings
ISBN (Electronic)	9781728133201
State	Published - 1 Jan 2020
Event	52nd IEEE International Symposium on Circuits and Systems, ISCAS 2020 - Virtual, Online Duration: 10 Oct 2020 → 21 Oct 2020

Publication series

Name	Proceedings - IEEE International Symposium on Circuits and Systems
Volume	2020-October

Conference

Conference	52nd IEEE International Symposium on Circuits and Systems, ISCAS 2020
City	Virtual, Online
Period	10/10/20 → 21/10/20

UN SDGs

This output contributes to the following UN Sustainable Development Goals (SDGs)

SDG 7 Affordable and Clean Energy

Keywords

Dual mode logic (DML)
Memory address decoder

All Science Journal Classification (ASJC) codes

Electrical and Electronic Engineering

Cite this

@inproceedings{71d5a5427fef44b9a32ce8061493d4ba,

title = "Dual mode logic address decoder",

abstract = "Address decoders are integral components of random access memories. In higher-performance computing, the timing of address decoders is often critical, especially in applications such as translation lookaside buffer (TLB) and first level data cache. On the other hand, memory power budget and energy consumption are equally critically important for battery-powered devices. Dual Mode Logic (DML) has been shown to combine the support for both requirements in a single circuit. We present a novel DML based address decoder design and compare it with conventional static CMOS and np-CMOS address decoders. Simulations show that DML based address decoder in dynamic mode achieves 31\% lower delay compared to conventional static CMOS implementation. In static mode, DML based address decoder reduces the energy consumption by 29\% and reaches 10\% lower energy-delay product compared to static CMOS address decoder. This is the first time DML is evaluated in 16nm FinFet process.",

keywords = "Dual mode logic (DML), Memory address decoder",

author = "Leonid Yavits and Ramiro Taco and Netanel Shavit and Inbal Stanger and Alexander Fish",

note = "Publisher Copyright: {\textcopyright} 2020 IEEE; 52nd IEEE International Symposium on Circuits and Systems, ISCAS 2020 ; Conference date: 10-10-2020 Through 21-10-2020",

year = "2020",

month = jan,

day = "1",

language = "American English",

series = "Proceedings - IEEE International Symposium on Circuits and Systems",

booktitle = "2020 IEEE International Symposium on Circuits and Systems, ISCAS 2020 - Proceedings",

}

Yavits, L, Taco, R, Shavit, N, Stanger, I & Fish, A 2020, Dual mode logic address decoder. in 2020 IEEE International Symposium on Circuits and Systems, ISCAS 2020 - Proceedings., 9180587, Proceedings - IEEE International Symposium on Circuits and Systems, vol. 2020-October, 52nd IEEE International Symposium on Circuits and Systems, ISCAS 2020, Virtual, Online, 10/10/20.

Dual mode logic address decoder. / Yavits, Leonid; Taco, Ramiro; Shavit, Netanel et al.
2020 IEEE International Symposium on Circuits and Systems, ISCAS 2020 - Proceedings. 2020. 9180587 (Proceedings - IEEE International Symposium on Circuits and Systems; Vol. 2020-October).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

TY - GEN

T1 - Dual mode logic address decoder

AU - Yavits, Leonid

AU - Taco, Ramiro

AU - Shavit, Netanel

AU - Stanger, Inbal

AU - Fish, Alexander

PY - 2020/1/1

Y1 - 2020/1/1

N2 - Address decoders are integral components of random access memories. In higher-performance computing, the timing of address decoders is often critical, especially in applications such as translation lookaside buffer (TLB) and first level data cache. On the other hand, memory power budget and energy consumption are equally critically important for battery-powered devices. Dual Mode Logic (DML) has been shown to combine the support for both requirements in a single circuit. We present a novel DML based address decoder design and compare it with conventional static CMOS and np-CMOS address decoders. Simulations show that DML based address decoder in dynamic mode achieves 31% lower delay compared to conventional static CMOS implementation. In static mode, DML based address decoder reduces the energy consumption by 29% and reaches 10% lower energy-delay product compared to static CMOS address decoder. This is the first time DML is evaluated in 16nm FinFet process.

AB - Address decoders are integral components of random access memories. In higher-performance computing, the timing of address decoders is often critical, especially in applications such as translation lookaside buffer (TLB) and first level data cache. On the other hand, memory power budget and energy consumption are equally critically important for battery-powered devices. Dual Mode Logic (DML) has been shown to combine the support for both requirements in a single circuit. We present a novel DML based address decoder design and compare it with conventional static CMOS and np-CMOS address decoders. Simulations show that DML based address decoder in dynamic mode achieves 31% lower delay compared to conventional static CMOS implementation. In static mode, DML based address decoder reduces the energy consumption by 29% and reaches 10% lower energy-delay product compared to static CMOS address decoder. This is the first time DML is evaluated in 16nm FinFet process.

KW - Dual mode logic (DML)

KW - Memory address decoder

UR - http://www.scopus.com/inward/record.url?scp=85106668183&partnerID=8YFLogxK

M3 - Conference contribution

T3 - Proceedings - IEEE International Symposium on Circuits and Systems

BT - 2020 IEEE International Symposium on Circuits and Systems, ISCAS 2020 - Proceedings

T2 - 52nd IEEE International Symposium on Circuits and Systems, ISCAS 2020

Y2 - 10 October 2020 through 21 October 2020

ER -

Dual mode logic address decoder

Abstract

Publication series

Conference

UN SDGs

Keywords

All Science Journal Classification (ASJC) codes

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Cite this