Dual-Layer Dielectric Stack for Thermally Isolated Low-Energy Phase-Change Memory

Scott W. Fong; Christopher M. Neumann; Eilam Yalon; Miguel Munoz Rojo; Eric Pop; H. S.Philip Wong

doi:https://doi.org/10.1109/TED.2017.2756071

Dual-Layer Dielectric Stack for Thermally Isolated Low-Energy Phase-Change Memory

Scott W. Fong, Christopher M. Neumann, Eilam Yalon, Miguel Munoz Rojo, Eric Pop, H. S.Philip Wong

Research output: Contribution to journal › Article › peer-review

Abstract

High reset energy is an ongoing issue for phase-change memory (PCM) devices. Prior work demonstrates that smaller PCM switching volume and thermal isolation can reduce the reset energy. In this paper, we fabricate and measure a planar confined PCM device with a multilayer dual-layer stack (DLS) of SiO₂/Al₂O₃ insulator. Devices with contact area of 500 to 20 nm and lengths of 2~ show exceptionally low reset energies of 18.25 ± 15.8 pJ and low reset current densities of 0.94 ± 0.51 MA/cm². Implementing the DLS enables a 60% reduction in reset energy compared with SiO₂-isolated devices.

Original language	English
Article number	8076849
Pages (from-to)	4496-4502
Number of pages	7
Journal	IEEE Transactions on Electron Devices
Volume	64
Issue number	11
DOIs	https://doi.org/10.1109/TED.2017.2756071
State	Published - Nov 2017
Externally published	Yes

Keywords

Phase-change memory (PCM)
reset energy
thermal conductivity
thermal design

All Science Journal Classification (ASJC) codes

Electronic, Optical and Magnetic Materials
Electrical and Electronic Engineering

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https://doi.org/10.1109/TED.2017.2756071

Cite this

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title = "Dual-Layer Dielectric Stack for Thermally Isolated Low-Energy Phase-Change Memory",

abstract = "High reset energy is an ongoing issue for phase-change memory (PCM) devices. Prior work demonstrates that smaller PCM switching volume and thermal isolation can reduce the reset energy. In this paper, we fabricate and measure a planar confined PCM device with a multilayer dual-layer stack (DLS) of SiO2/Al2O3 insulator. Devices with contact area of 500 to 20 nm and lengths of 2~ show exceptionally low reset energies of 18.25 ± 15.8 pJ and low reset current densities of 0.94 ± 0.51 MA/cm2. Implementing the DLS enables a 60% reduction in reset energy compared with SiO2-isolated devices.",

keywords = "Phase-change memory (PCM), reset energy, thermal conductivity, thermal design",

author = "Fong, {Scott W.} and Neumann, {Christopher M.} and Eilam Yalon and Rojo, {Miguel Munoz} and Eric Pop and Wong, {H. S.Philip}",

note = "Publisher Copyright: {\textcopyright} 1963-2012 IEEE.",

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doi = "https://doi.org/10.1109/TED.2017.2756071",

language = "الإنجليزيّة",

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T1 - Dual-Layer Dielectric Stack for Thermally Isolated Low-Energy Phase-Change Memory

AU - Fong, Scott W.

AU - Neumann, Christopher M.

AU - Yalon, Eilam

AU - Rojo, Miguel Munoz

AU - Pop, Eric

AU - Wong, H. S.Philip

PY - 2017/11

Y1 - 2017/11

N2 - High reset energy is an ongoing issue for phase-change memory (PCM) devices. Prior work demonstrates that smaller PCM switching volume and thermal isolation can reduce the reset energy. In this paper, we fabricate and measure a planar confined PCM device with a multilayer dual-layer stack (DLS) of SiO2/Al2O3 insulator. Devices with contact area of 500 to 20 nm and lengths of 2~ show exceptionally low reset energies of 18.25 ± 15.8 pJ and low reset current densities of 0.94 ± 0.51 MA/cm2. Implementing the DLS enables a 60% reduction in reset energy compared with SiO2-isolated devices.

AB - High reset energy is an ongoing issue for phase-change memory (PCM) devices. Prior work demonstrates that smaller PCM switching volume and thermal isolation can reduce the reset energy. In this paper, we fabricate and measure a planar confined PCM device with a multilayer dual-layer stack (DLS) of SiO2/Al2O3 insulator. Devices with contact area of 500 to 20 nm and lengths of 2~ show exceptionally low reset energies of 18.25 ± 15.8 pJ and low reset current densities of 0.94 ± 0.51 MA/cm2. Implementing the DLS enables a 60% reduction in reset energy compared with SiO2-isolated devices.

KW - Phase-change memory (PCM)

KW - reset energy

KW - thermal conductivity

KW - thermal design

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M3 - مقالة

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EP - 4502

JO - IEEE Transactions on Electron Devices

JF - IEEE Transactions on Electron Devices

IS - 11

M1 - 8076849

ER -

Dual-Layer Dielectric Stack for Thermally Isolated Low-Energy Phase-Change Memory

Abstract

Keywords

All Science Journal Classification (ASJC) codes

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