DML Energy-Delay Tradeoffs and Optimization

Itamar Levi; Alexander Fish

doi:https://doi.org/10.1007/978-3-030-40786-5_5

DML Energy-Delay Tradeoffs and Optimization

Itamar Levi, Alexander Fish

Bar-Ilan University

Research output: Chapter in Book/Report/Conference proceeding › Chapter

Abstract

As shown in the previous chapters, DML design provides very high energy-delay (E-D) optimization flexibility at the gate level. In this chapter, this flexibility is utilized to enhance the energy efficiency and performance of larger combinatorial circuits. In other...

Original language	English
Title of host publication	Dual Mode Logic
Place of Publication	Cham, Switzerland
Pages	75-87
Number of pages	13
DOIs	https://doi.org/10.1007/978-3-030-40786-5_5
State	Published - 16 Dec 2020

Keywords

Adder
Carry Look-Ahead (CLA)
Carry Save Adder (CSA)
Carry propagation
Critical path (CP)
DML
Energy efficiency
High performance
Input vector
Ripple carry adder (RCA)

UN SDGs

This output contributes to the following UN Sustainable Development Goals (SDGs)

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https://doi.org/10.1007/978-3-030-40786-5_5

Cite this

@inbook{5d4fd85f5529429d9f48d3b6293bf9ad,

title = "DML Energy-Delay Tradeoffs and Optimization",

abstract = "As shown in the previous chapters, DML design provides very high energy-delay (E-D) optimization flexibility at the gate level. In this chapter, this flexibility is utilized to enhance the energy efficiency and performance of larger combinatorial circuits. In other...",

keywords = "Adder, Carry Look-Ahead (CLA), Carry Save Adder (CSA), Carry propagation, Critical path (CP), DML, Energy efficiency, High performance, Input vector, Ripple carry adder (RCA)",

author = "Itamar Levi and Alexander Fish",

year = "2020",

month = dec,

day = "16",

doi = "https://doi.org/10.1007/978-3-030-40786-5_5",

language = "الإنجليزيّة",

pages = "75--87",

booktitle = "Dual Mode Logic",

}

TY - CHAP

T1 - DML Energy-Delay Tradeoffs and Optimization

AU - Levi, Itamar

AU - Fish, Alexander

PY - 2020/12/16

Y1 - 2020/12/16

N2 - As shown in the previous chapters, DML design provides very high energy-delay (E-D) optimization flexibility at the gate level. In this chapter, this flexibility is utilized to enhance the energy efficiency and performance of larger combinatorial circuits. In other...

AB - As shown in the previous chapters, DML design provides very high energy-delay (E-D) optimization flexibility at the gate level. In this chapter, this flexibility is utilized to enhance the energy efficiency and performance of larger combinatorial circuits. In other...

KW - Adder

KW - Carry Look-Ahead (CLA)

KW - Carry Save Adder (CSA)

KW - Carry propagation

KW - Critical path (CP)

KW - DML

KW - Energy efficiency

KW - High performance

KW - Input vector

KW - Ripple carry adder (RCA)

UR - https://www.mendeley.com/catalogue/6580ece9-d8e6-3995-ae97-58e0b29c7bf2/

U2 - https://doi.org/10.1007/978-3-030-40786-5_5

DO - https://doi.org/10.1007/978-3-030-40786-5_5

M3 - فصل

SP - 75

EP - 87

BT - Dual Mode Logic

CY - Cham, Switzerland

ER -

DML Energy-Delay Tradeoffs and Optimization

Abstract

Keywords

UN SDGs

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