TY - GEN
T1 - Digital Controller for High-Performance Multiphase VRM with Current Balancing and Near-Ideal Transient Response
AU - Halivni, Bar
AU - Peretz, Mor Mordechai
N1 - Publisher Copyright: © 2020 IEEE.
PY - 2020/3/1
Y1 - 2020/3/1
N2 - This paper introduces a digital current-programmed control for multiphase buck VRM for high-performance loads that regulates the output voltage with high accuracy, maintains current sharing of all phases for the entire operation range, and achieves optimal transient recovery for load transients. These are enabled by hybrid controller architecture that facilitates perphase average current control (ACM) for steady-state operation and a state-space based transient oriented controller that executes time-optimal or minimum-deviation recovery for loading and unloading transients. Active voltage positioning (AVP) as well as current sharing algorithms are embedded, covering all the required features to supply modern high-end loads. In addition to the high-end analog interface developed for accurate acquisition of the control signals, the digital core IP blocks (compensation, sharing, droop, etc.) and peripheral units (HRDPWM, ADC) are realized by combinatorial asynchronous logic, all with standard cells using HDL toward direct synthesis for IC implementation. The resultant compact controller (implemented on FPGA with total logic element count of 1700 elements for 4 phases) has been tested and successfully validated experimentally on Intel-certified hardware. The experimental prototype featured a 4-phase 12V to 1.xV buck VRM that drives an array of 7 DDR4 load modules, accommodating 100A load transients with transition rate of 1000A/μs, and demonstrating time-optimal recovery.
AB - This paper introduces a digital current-programmed control for multiphase buck VRM for high-performance loads that regulates the output voltage with high accuracy, maintains current sharing of all phases for the entire operation range, and achieves optimal transient recovery for load transients. These are enabled by hybrid controller architecture that facilitates perphase average current control (ACM) for steady-state operation and a state-space based transient oriented controller that executes time-optimal or minimum-deviation recovery for loading and unloading transients. Active voltage positioning (AVP) as well as current sharing algorithms are embedded, covering all the required features to supply modern high-end loads. In addition to the high-end analog interface developed for accurate acquisition of the control signals, the digital core IP blocks (compensation, sharing, droop, etc.) and peripheral units (HRDPWM, ADC) are realized by combinatorial asynchronous logic, all with standard cells using HDL toward direct synthesis for IC implementation. The resultant compact controller (implemented on FPGA with total logic element count of 1700 elements for 4 phases) has been tested and successfully validated experimentally on Intel-certified hardware. The experimental prototype featured a 4-phase 12V to 1.xV buck VRM that drives an array of 7 DDR4 load modules, accommodating 100A load transients with transition rate of 1000A/μs, and demonstrating time-optimal recovery.
KW - DDR
KW - Digital control
KW - VRM
KW - buck
KW - controller
KW - hybrid control
KW - multiphase
UR - http://www.scopus.com/inward/record.url?scp=85087761491&partnerID=8YFLogxK
U2 - 10.1109/APEC39645.2020.9124261
DO - 10.1109/APEC39645.2020.9124261
M3 - Conference contribution
T3 - Conference Proceedings - IEEE Applied Power Electronics Conference and Exposition - APEC
SP - 2206
EP - 2213
BT - APEC 2020 - 35th Annual IEEE Applied Power Electronics Conference and Exposition
T2 - 35th Annual IEEE Applied Power Electronics Conference and Exposition, APEC 2020
Y2 - 15 March 2020 through 19 March 2020
ER -