DiDi: Mitigating the performance impact of TLB shootdowns using a shared TLB directory

Carlos Villavieja, Vasileios Karakostas, Lluis Vilanova, Yoav Etsion, Alex Ramirez, Avi Mendelson, Nacho Navarro, Adrián Cristal, Osman S. Unsal

Research output: Chapter in Book/Report/Conference proceedingConference contributionpeer-review

Abstract

Translation Lookaside Buffers (TLBs) are ubiquitously used in modern architectures to cache virtual-to-physical mappings and, as they are looked up on every memory access, are paramount to performance scalability. The emergence of chipmultiprocessors (CMPs) with per-core TLBs, has brought the problem of TLB coherence to front stage. TLBs are kept coherent at the software-level by the operating system (OS). Whenever the OS modifies page permissions in a page table, it must initiate a coherency transaction among TLBs, a process known as a TLB shootdown. Current CMPs rely on the OS to approximate the set of TLBs caching a mapping and synchronize TLBs using costly Inter-Proceessor Interrupts (IPIs) and software handlers. In this paper, we characterize the impact of TLB shootdowns on multiprocessor performance and scalability, and present the design of a scalable TLB coherency mechanism. First, we show that both TLB shootdown cost and frequency increase with the number of processors and project that softwarebased TLB shootdowns would thwart the performance of large multiprocessors. We then present a scalable architectural mechanism that couples a shared TLB directory with load/store queue support for lightweight TLB invalidation, and thereby eliminates the need for costly IPIs. Finally, we show that the proposed mechanism reduces the fraction of machine cycles wasted on TLB shootdowns by an order of magnitude.

Original languageEnglish
Title of host publicationProceedings - 2011 International Conference on Parallel Architectures and Compilation Techniques, PACT 2011
Pages340-349
Number of pages10
DOIs
StatePublished - 2011
Externally publishedYes
Event20th International Conference on Parallel Architectures and Compilation Techniques, PACT 2011 - Galveston, TX, United States
Duration: 10 Oct 201114 Oct 2011

Publication series

NameParallel Architectures and Compilation Techniques - Conference Proceedings, PACT

Conference

Conference20th International Conference on Parallel Architectures and Compilation Techniques, PACT 2011
Country/TerritoryUnited States
CityGalveston, TX
Period10/10/1114/10/11

All Science Journal Classification (ASJC) codes

  • Software
  • Theoretical Computer Science
  • Hardware and Architecture

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