TY - GEN
T1 - Design patterns for code reuse in hls packet processing pipelines
AU - Eran, Haggai
AU - Zeno, Lior
AU - Istvan, Zsolt
AU - Silberstein, Mark
N1 - Publisher Copyright: © 2019 IEEE.
PY - 2019/4
Y1 - 2019/4
N2 - High-level synthesis (HLS) allows developers to be more productive in designing FPGA circuits thanks to familiar programming languages and high-level abstractions. In order to create high-performance circuits, HLS tools, such as Xilinx Vivado HLS, require following specific design patterns and techniques. Unfortunately, when applied to network packet processing tasks, these techniques limit code reuse and modularity, requiring developers to use deprecated programming conventions. We propose a methodology for developing high-speed networking applications using Vivado HLS for C++, focusing on reusability, code simplicity, and overall performance. Following this methodology, we implement a class library (ntl) with several building blocks that can be used in a wide spectrum of networking applications. We evaluate the methodology by implementing two applications: A UDP stateless firewall and a key-value store cache designed for FPGA-based SmartNICs, both processing packets at 40Gbps line-rate.
AB - High-level synthesis (HLS) allows developers to be more productive in designing FPGA circuits thanks to familiar programming languages and high-level abstractions. In order to create high-performance circuits, HLS tools, such as Xilinx Vivado HLS, require following specific design patterns and techniques. Unfortunately, when applied to network packet processing tasks, these techniques limit code reuse and modularity, requiring developers to use deprecated programming conventions. We propose a methodology for developing high-speed networking applications using Vivado HLS for C++, focusing on reusability, code simplicity, and overall performance. Following this methodology, we implement a class library (ntl) with several building blocks that can be used in a wide spectrum of networking applications. We evaluate the methodology by implementing two applications: A UDP stateless firewall and a key-value store cache designed for FPGA-based SmartNICs, both processing packets at 40Gbps line-rate.
KW - Design methodology
KW - High level synthesis
KW - Networking
KW - Packet processing
UR - http://www.scopus.com/inward/record.url?scp=85068333756&partnerID=8YFLogxK
U2 - 10.1109/FCCM.2019.00036
DO - 10.1109/FCCM.2019.00036
M3 - منشور من مؤتمر
T3 - Proceedings - 27th IEEE International Symposium on Field-Programmable Custom Computing Machines, FCCM 2019
SP - 208
EP - 217
BT - Proceedings - 27th IEEE International Symposium on Field-Programmable Custom Computing Machines, FCCM 2019
T2 - 27th Annual IEEE International Symposium on Field-Programmable Custom Computing Machines, FCCM 2019
Y2 - 28 April 2019 through 1 May 2019
ER -