@inproceedings{cc4508f88c3f418f8e47be5f2736df25,
title = "Design methodology for stateful memristive logic gates",
abstract = "Memristors are passive, two terminal, circuit elements with a resistance which depends on a state variable, and changes according to the voltage applied across the device. Alongside the natural use of memristors as memory, using these devices as building blocks for logic gates is widely researched. In this paper, a structured design methodology is presented to assist in the development of a class of such logic gates - 'stateful' logic, in which the memristor resistance is used as a logic value. The methodology is demonstrated by two examples, the first resulting in a recreation of the previously published MAGIC NOR gate, with the addition of NAND functionality on the same topology. In the second example, a novel gate is presented, realizing OR and XOR logic functions using non-polar memristors.",
keywords = "MAGIC, design methodology, in-memory computing, memory processing unit (MPU), memristor, resistive switch, stateful logic",
author = "Nimrod Wald and Shahar Kvatinsky",
note = "Publisher Copyright: {\textcopyright} 2016 IEEE.; 2016 IEEE International Conference on the Science of Electrical Engineering, ICSEE 2016 ; Conference date: 16-11-2016 Through 18-11-2016",
year = "2017",
month = jan,
day = "4",
doi = "10.1109/ICSEE.2016.7806155",
language = "الإنجليزيّة",
series = "2016 IEEE International Conference on the Science of Electrical Engineering, ICSEE 2016",
booktitle = "2016 IEEE International Conference on the Science of Electrical Engineering, ICSEE 2016",
}