TY - GEN
T1 - Design and IC implementation of a fully digital power management delay-line ADC
AU - Bezdenezhnykh, Yevgeny
AU - Vekslender, Timur
AU - Abramov, Eli
AU - Cervera, Alon
AU - Peretz, Mor Mordechai
N1 - Publisher Copyright: © Copyright 2015 IEEE All rights reserved.
PY - 2014/1/1
Y1 - 2014/1/1
N2 - This paper presents the design and IC implementation of a fully-digital 10-bit, 4Mbps sampling rate, delay-line analog-to-digital converter (DL-ADC) for power management applications. The design of the ADC is based on the approach of delay cells string to reduce design complexity and the resultant the silicon area. A unique advantage of the new ADC architecture and the design process is that it is entirely based on standard digital cells out of a vendor's library. Namely, neither custom nor analog design is required, making the concept attractive in terms of performance, scalability to other implementation platforms, design complexity and cost. In this study, two implementation options to the DL-ADC architecture are presented, and both are demonstrated and verified with post-layout results on a Tower Jazz 0.18μm power management (TS18PM) platform. The total silicon area that is required for the implementation of the new DL-ADC sums at 0.05mm2, which confirms the area saving attribute of the concept and design procedure.
AB - This paper presents the design and IC implementation of a fully-digital 10-bit, 4Mbps sampling rate, delay-line analog-to-digital converter (DL-ADC) for power management applications. The design of the ADC is based on the approach of delay cells string to reduce design complexity and the resultant the silicon area. A unique advantage of the new ADC architecture and the design process is that it is entirely based on standard digital cells out of a vendor's library. Namely, neither custom nor analog design is required, making the concept attractive in terms of performance, scalability to other implementation platforms, design complexity and cost. In this study, two implementation options to the DL-ADC architecture are presented, and both are demonstrated and verified with post-layout results on a Tower Jazz 0.18μm power management (TS18PM) platform. The total silicon area that is required for the implementation of the new DL-ADC sums at 0.05mm2, which confirms the area saving attribute of the concept and design procedure.
KW - Delay-line ADC
KW - Digital implementation
KW - Integrated circuit design
UR - http://www.scopus.com/inward/record.url?scp=84941242080&partnerID=8YFLogxK
U2 - 10.1109/EEEI.2014.7005750
DO - 10.1109/EEEI.2014.7005750
M3 - Conference contribution
T3 - 2014 IEEE 28th Convention of Electrical and Electronics Engineers in Israel, IEEEI 2014
BT - 2014 IEEE 28th Convention of Electrical and Electronics Engineers in Israel, IEEEI 2014
T2 - 2014 28th IEEE Convention of Electrical and Electronics Engineers in Israel, IEEEI 2014
Y2 - 3 December 2014 through 5 December 2014
ER -