Delayed stochastic decoding of LDPC codes

Ali Naderi; Shie Mannor; Mohamad Sawan; Warren J. Gross

doi:https://doi.org/10.1109/TSP.2011.2163630

Delayed stochastic decoding of LDPC codes

Ali Naderi, Shie Mannor, Mohamad Sawan, Warren J. Gross

Technion - Israel Institute of Technology

Research output: Contribution to journal › Article › peer-review

Abstract

A new stochastic decoding algorithm, called Delayed Stochastic (DS) decoding, is introduced to implement low-density-parity-check (LDPC) decoders. The delayed stochastic decoding uses an alternative method to track probability values, which results in reduction of hardware complexity and memory requirement of the stochastic decoders. It is therefore suitable for fully-parallel implementation of long LDPC codes with applications in optical communications. Two decoders are implemented using the DS algorithm for medium (2048, 1723) and long (32768, 26624) LDPC codes. The decoders occupy 3.93-mm² and 56.5-mm² silicon area using 90-nm CMOS technology and provide maximum core throughputs of 172.4 and 477.7 Gb/s at E_b/N_o=5.5 and 4.8 dB, respectively.

Original language	English
Article number	5975253
Pages (from-to)	5617-5626
Number of pages	10
Journal	IEEE Transactions on Signal Processing
Volume	59
Issue number	11
DOIs	https://doi.org/10.1109/TSP.2011.2163630
State	Published - Nov 2011

Keywords

Delayed stochastic decoding
iterative decoding
low-density parity-check code
stochastic decoding

All Science Journal Classification (ASJC) codes

Signal Processing
Electrical and Electronic Engineering

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title = "Delayed stochastic decoding of LDPC codes",

abstract = "A new stochastic decoding algorithm, called Delayed Stochastic (DS) decoding, is introduced to implement low-density-parity-check (LDPC) decoders. The delayed stochastic decoding uses an alternative method to track probability values, which results in reduction of hardware complexity and memory requirement of the stochastic decoders. It is therefore suitable for fully-parallel implementation of long LDPC codes with applications in optical communications. Two decoders are implemented using the DS algorithm for medium (2048, 1723) and long (32768, 26624) LDPC codes. The decoders occupy 3.93-mm2 and 56.5-mm2 silicon area using 90-nm CMOS technology and provide maximum core throughputs of 172.4 and 477.7 Gb/s at Eb/No=5.5 and 4.8 dB, respectively.",

keywords = "Delayed stochastic decoding, iterative decoding, low-density parity-check code, stochastic decoding",

author = "Ali Naderi and Shie Mannor and Mohamad Sawan and Gross, {Warren J.}",

note = "Funding Information: Manuscript received December 15, 2010; revised April 04, 2011 and July 13, 2011; accepted July 14, 2011. Date of publication August 04, 2011; date of current version October 12, 2011. The associate editor coordinating the review of this manuscript and approving it for publication was Dr. Tong Zhang. The authors would like to thank the Natural Sciences and Engineering Research Council of Canada (NSERC), Regroupement Strategique en Microsystemes du Quebec (RESMIQ), CMC Microsystems and Western Canada Research Grid (WestGrid) for financial support and design tools.",

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doi = "https://doi.org/10.1109/TSP.2011.2163630",

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AU - Naderi, Ali

AU - Mannor, Shie

AU - Sawan, Mohamad

AU - Gross, Warren J.

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AB - A new stochastic decoding algorithm, called Delayed Stochastic (DS) decoding, is introduced to implement low-density-parity-check (LDPC) decoders. The delayed stochastic decoding uses an alternative method to track probability values, which results in reduction of hardware complexity and memory requirement of the stochastic decoders. It is therefore suitable for fully-parallel implementation of long LDPC codes with applications in optical communications. Two decoders are implemented using the DS algorithm for medium (2048, 1723) and long (32768, 26624) LDPC codes. The decoders occupy 3.93-mm2 and 56.5-mm2 silicon area using 90-nm CMOS technology and provide maximum core throughputs of 172.4 and 477.7 Gb/s at Eb/No=5.5 and 4.8 dB, respectively.

KW - Delayed stochastic decoding

KW - iterative decoding

KW - low-density parity-check code

KW - stochastic decoding

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JF - IEEE Transactions on Signal Processing

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ER -

Delayed stochastic decoding of LDPC codes

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Keywords

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