TY - JOUR
T1 - Concept
T2 - A column-oriented memory controller for efficient memory and PIM operations in RRAM
AU - Talati, Nishil
AU - Ha, Heonjae
AU - Perach, Ben
AU - Ronen, Ronny
AU - Kvatinsky, Shahar
N1 - Funding Information: This work was carried out when the first author was at the Technion-Israel Institute of Technology. This work was supported in part by the European Research Council under the European Union's Horizon 2020 Research and Innovation Programme under Grant 757259, in part by the Viterbi Fellowship at the Technion Computer Engineering Center, in part by the EU ICT COST Action IC1401, and in part by the Israel Science Foundation under Grant 1514/17. Funding Information: This work was carried out when the first author was at the Technion—Israel Institute of Technology. This work was supported in part by the European Research Council under the European Union’s Horizon 2020 Research and Innovation Programme under Grant 757259, in part by the Viterbi Fellowship at the Technion Computer Engineering Center, in part by the EU ICT COST Action IC1401, and in part by the Israel Science Foundation under Grant 1514/17. Publisher Copyright: © 2019 IEEE. All Rights Reserved.
PY - 2019/1/1
Y1 - 2019/1/1
N2 - While DRAM cannot easily scale below a 20-nm technology node, RRAM suffers far less from scalability issues. Moreover, RRAM's resistivity enables its use for processing-in-memory (PIM), potentially alleviating the von Neumann bottleneck. Unfortunately, because of technological idiosyncrasies, existing DRAM-centric memory controllers cannot exploit the full potential of resistive RAM (RRAM). In this paper, we present the design of a memory controller called CONCEPT. The controller is optimized to exploit unique properties of RRAM to enhance its performance and energy efficiency as well as exploiting RRAM's PIM capability. We show that with CONCEPT, RRAM can achieve DRAM-like performance and energy efficiency on SPEC CPU 2006 benchmarks. Furthermore, using RRAM PIM capabilities, we show a 5 performance gain on a data-intensive in-memory database workload compared to a state-of-the-art CPU-memory computing model.
AB - While DRAM cannot easily scale below a 20-nm technology node, RRAM suffers far less from scalability issues. Moreover, RRAM's resistivity enables its use for processing-in-memory (PIM), potentially alleviating the von Neumann bottleneck. Unfortunately, because of technological idiosyncrasies, existing DRAM-centric memory controllers cannot exploit the full potential of resistive RAM (RRAM). In this paper, we present the design of a memory controller called CONCEPT. The controller is optimized to exploit unique properties of RRAM to enhance its performance and energy efficiency as well as exploiting RRAM's PIM capability. We show that with CONCEPT, RRAM can achieve DRAM-like performance and energy efficiency on SPEC CPU 2006 benchmarks. Furthermore, using RRAM PIM capabilities, we show a 5 performance gain on a data-intensive in-memory database workload compared to a state-of-the-art CPU-memory computing model.
UR - https://www.scopus.com/pages/publications/85059479798
U2 - 10.1109/MM.2018.2890033
DO - 10.1109/MM.2018.2890033
M3 - Article
SN - 0272-1732
VL - 39
SP - 33
EP - 43
JO - IEEE Micro
JF - IEEE Micro
IS - 1
M1 - 8600341
ER -
SDG 7 Affordable and Clean Energy