Codes for high performance write and read processes in multi-level NVMs

Evyatar Hemo, Yuval Cassuto

Research output: Chapter in Book/Report/Conference proceedingConference contributionpeer-review

Abstract

Multi-level memory cells are used in non-volatile memories in order to increase the storage density. Using multi-level cells, however, imposes higher read and write latencies limiting high speed applications. In this work we study the tradeoff between storage density and write/read performance using codes. The contributions are codes that give high-performance write and read processes with minimal reduction in storage density. We describe the codes, give an analytical treatment of their information rate and speed, and compare them with more basic access schemes and upper bounds.

Original languageEnglish
Title of host publication2014 IEEE International Symposium on Information Theory, ISIT 2014
Pages2092-2096
Number of pages5
DOIs
StatePublished - 2014
Event2014 IEEE International Symposium on Information Theory, ISIT 2014 - Honolulu, HI, United States
Duration: 29 Jun 20144 Jul 2014

Publication series

NameIEEE International Symposium on Information Theory - Proceedings

Conference

Conference2014 IEEE International Symposium on Information Theory, ISIT 2014
Country/TerritoryUnited States
CityHonolulu, HI
Period29/06/144/07/14

All Science Journal Classification (ASJC) codes

  • Theoretical Computer Science
  • Information Systems
  • Modelling and Simulation
  • Applied Mathematics

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