Asynchronous signalling processes

Rajit Manohar, Yoram Moses

Research output: Chapter in Book/Report/Conference proceedingConference contributionpeer-review

Abstract

A model of processes that interact via asynchronous wires carrying Boolean signals is presented. In this model, modules, called processes, can be made arbitrarily complex, can maintain local memory and can have an arbitrary number of inputs and outputs. A variety of circuit models can be represented by networks of signalling processes. It is shown that in a network of signalling processes consisting solely of single-ouput processes and forks, every module is an eventual C element. Consequently, the computational power of such a network is severely limited. This establishes that the celebrated C-element property of DI circuits follows solely from the fact that single output modules communicate over stable asynchronous wires. Conversely, it is shown that any Boolean function can be implemented using four input/two-output processes where every process is either one gate (single output) or a pair of gates (two output).

Original languageEnglish
Title of host publicationProceedings - 2019 25th IEEE International Symposium on Asynchronous Circuits and Systems, ASYNC 2019
Pages68-75
Number of pages8
ISBN (Electronic)9781538647479
DOIs
StatePublished - May 2019
Event25th IEEE International Symposium on Asynchronous Circuits and Systems, ASYNC 2019 - Hirosaki, Japan
Duration: 12 May 201915 May 2019

Publication series

NameProceedings - International Symposium on Asynchronous Circuits and Systems
Volume2019-May

Conference

Conference25th IEEE International Symposium on Asynchronous Circuits and Systems, ASYNC 2019
Country/TerritoryJapan
CityHirosaki
Period12/05/1915/05/19

Keywords

  • Delay insensitive circuits

All Science Journal Classification (ASJC) codes

  • Electrical and Electronic Engineering

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