TY - JOUR
T1 - Analysis of the task superscalar architecture hardware design
AU - Yazdanpanah, Fahimeh
AU - Jimenez-Gonzalez, Daniel
AU - Alvarez-Martinez, Carlos
AU - Etsion, Yoav
AU - Badia, Rosa M.
N1 - Funding Information: This work is supported by the Ministry of Science and Technology of Spain and the European Union (FEDER funds) under contract TIN2007-60625, by the Generalitat de Catalunya (contract 2009-SGR-980), and by the European FP7 project TERAFLUX id. 249013, http://www.teraflux.eu. We would also like to thank the Xilinx University Program for its hardware and software donations.
PY - 2013
Y1 - 2013
N2 - In this paper, we analyze the operational flow of two hardware implementations of the Task Superscalar architecture. The Task Superscalar is an experimental task based dataflow scheduler that dynamically detects inter-task data dependencies, identifies task-level parallelism, and executes tasks in the out-of-order manner. In this paper, we present a base implementation of the Task Superscalar architecture, as well as a new design with improved performance. We study the behavior of processing some dependent and non-dependent tasks with both base and improved hardware designs and present the simulation results compared with the results of the runtime implementation.
AB - In this paper, we analyze the operational flow of two hardware implementations of the Task Superscalar architecture. The Task Superscalar is an experimental task based dataflow scheduler that dynamically detects inter-task data dependencies, identifies task-level parallelism, and executes tasks in the out-of-order manner. In this paper, we present a base implementation of the Task Superscalar architecture, as well as a new design with improved performance. We study the behavior of processing some dependent and non-dependent tasks with both base and improved hardware designs and present the simulation results compared with the results of the runtime implementation.
KW - Hardware task scheduler
KW - Task superscalar
KW - VHDL
UR - http://www.scopus.com/inward/record.url?scp=84896949372&partnerID=8YFLogxK
U2 - https://doi.org/10.1016/j.procs.2013.05.197
DO - https://doi.org/10.1016/j.procs.2013.05.197
M3 - مقالة من مؤنمر
SN - 1877-0509
VL - 18
SP - 339
EP - 348
JO - Procedia Computer Science
JF - Procedia Computer Science
T2 - 13th Annual International Conference on Computational Science, ICCS 2013
Y2 - 5 June 2013 through 7 June 2013
ER -