Analysis of the task superscalar architecture hardware design

Fahimeh Yazdanpanah, Daniel Jimenez-Gonzalez, Carlos Alvarez-Martinez, Yoav Etsion, Rosa M. Badia

Research output: Contribution to journalConference articlepeer-review


In this paper, we analyze the operational flow of two hardware implementations of the Task Superscalar architecture. The Task Superscalar is an experimental task based dataflow scheduler that dynamically detects inter-task data dependencies, identifies task-level parallelism, and executes tasks in the out-of-order manner. In this paper, we present a base implementation of the Task Superscalar architecture, as well as a new design with improved performance. We study the behavior of processing some dependent and non-dependent tasks with both base and improved hardware designs and present the simulation results compared with the results of the runtime implementation.

Original languageEnglish
Pages (from-to)339-348
Number of pages10
JournalProcedia Computer Science
StatePublished - 2013
Event13th Annual International Conference on Computational Science, ICCS 2013 - Barcelona, Spain
Duration: 5 Jun 20137 Jun 2013


  • Hardware task scheduler
  • Task superscalar
  • VHDL

All Science Journal Classification (ASJC) codes

  • Computer Science(all)


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