Analysis and Design of N-Path True-Time-Delay Circuit

Integrated true-time-delay (TTD) cells for RF frequencies are usually large and have high relative delay variation. Here, the $N$ -path TTD topology is explored, where the signal is undersampled with a number of parallel S/H circuits and reconstructed and summed after a given time delay. This topology allows the improvement of the delay-bandwidth (DBW) limit and provides minimum variation in time delay while requiring relatively small area and power. The effect of the TTD is analyzed with a linear periodic time-variant mathematical model and is verified through simulations and measurements. Measurements of 65-nm CMOS chip implementation show up to 2-ns delay for a bandwidth of 400 MHz with maximum delay variation over frequency of 10 ps and power consumption of 9.6 mW.