An SRAM PUF with 2 independent bits/cell in 65nm

Yizhak Shifman; Avi Miller; Yoav Weizman; Alexander Fish; Joseph Shor

doi:https://doi.org/10.1109/ISCAS.2019.8702612

An SRAM PUF with 2 independent bits/cell in 65nm

Yizhak Shifman, Avi Miller, Yoav Weizman, Alexander Fish, Joseph Shor

Bar-Ilan University - The Alexander Kofkin Faculty of Engineering

Bar-Ilan University

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

Abstract

An SRAM Physical Unclonable Function (PUF) cell is fabricated and reported, which has two bits per cell. The Decision Voltage of the cell is analyzed and the cell is designed such that only the NMOS devices in the latch configuration contribute to the cell response. Either one of two pairs of NMOS devices is selected, such that two independent bits are generated. The cell was fabricated and measured in TSMC 65nm technology with a highly competitive area of 1420F² per bit.

Original language	English
Title of host publication	2019 IEEE International Symposium on Circuits and Systems, ISCAS 2019 - Proceedings
Publisher	Institute of Electrical and Electronics Engineers Inc.
ISBN (Electronic)	9781728103976
DOIs	https://doi.org/10.1109/ISCAS.2019.8702612
State	Published - 1 Jan 2019
Event	2019 IEEE International Symposium on Circuits and Systems, ISCAS 2019 - Sapporo, Japan Duration: 26 May 2019 → 29 May 2019

Publication series

Name	Proceedings - IEEE International Symposium on Circuits and Systems
Volume	2019-May

Conference

Conference	2019 IEEE International Symposium on Circuits and Systems, ISCAS 2019
Country/Territory	Japan
City	Sapporo
Period	26/05/19 → 29/05/19

Keywords

PUF
Physical Unclonable Function
SRAM

All Science Journal Classification (ASJC) codes

Electrical and Electronic Engineering

Access to Document

https://doi.org/10.1109/ISCAS.2019.8702612

Cite this

Shifman, Y., Miller, A., Weizman, Y., Fish, A., & Shor, J. (2019). An SRAM PUF with 2 independent bits/cell in 65nm. In 2019 IEEE International Symposium on Circuits and Systems, ISCAS 2019 - Proceedings Article 8702612 (Proceedings - IEEE International Symposium on Circuits and Systems; Vol. 2019-May). Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.1109/ISCAS.2019.8702612

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title = "An SRAM PUF with 2 independent bits/cell in 65nm",

abstract = "An SRAM Physical Unclonable Function (PUF) cell is fabricated and reported, which has two bits per cell. The Decision Voltage of the cell is analyzed and the cell is designed such that only the NMOS devices in the latch configuration contribute to the cell response. Either one of two pairs of NMOS devices is selected, such that two independent bits are generated. The cell was fabricated and measured in TSMC 65nm technology with a highly competitive area of 1420F2 per bit.",

keywords = "PUF, Physical Unclonable Function, SRAM",

author = "Yizhak Shifman and Avi Miller and Yoav Weizman and Alexander Fish and Joseph Shor",

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year = "2019",

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language = "الإنجليزيّة",

series = "Proceedings - IEEE International Symposium on Circuits and Systems",

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Shifman, Y, Miller, A, Weizman, Y, Fish, A & Shor, J 2019, An SRAM PUF with 2 independent bits/cell in 65nm. in 2019 IEEE International Symposium on Circuits and Systems, ISCAS 2019 - Proceedings., 8702612, Proceedings - IEEE International Symposium on Circuits and Systems, vol. 2019-May, Institute of Electrical and Electronics Engineers Inc., 2019 IEEE International Symposium on Circuits and Systems, ISCAS 2019, Sapporo, Japan, 26/05/19. https://doi.org/10.1109/ISCAS.2019.8702612

An SRAM PUF with 2 independent bits/cell in 65nm. / Shifman, Yizhak; Miller, Avi; Weizman, Yoav et al.
2019 IEEE International Symposium on Circuits and Systems, ISCAS 2019 - Proceedings. Institute of Electrical and Electronics Engineers Inc., 2019. 8702612 (Proceedings - IEEE International Symposium on Circuits and Systems; Vol. 2019-May).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

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AU - Weizman, Yoav

AU - Fish, Alexander

AU - Shor, Joseph

PY - 2019/1/1

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N2 - An SRAM Physical Unclonable Function (PUF) cell is fabricated and reported, which has two bits per cell. The Decision Voltage of the cell is analyzed and the cell is designed such that only the NMOS devices in the latch configuration contribute to the cell response. Either one of two pairs of NMOS devices is selected, such that two independent bits are generated. The cell was fabricated and measured in TSMC 65nm technology with a highly competitive area of 1420F2 per bit.

AB - An SRAM Physical Unclonable Function (PUF) cell is fabricated and reported, which has two bits per cell. The Decision Voltage of the cell is analyzed and the cell is designed such that only the NMOS devices in the latch configuration contribute to the cell response. Either one of two pairs of NMOS devices is selected, such that two independent bits are generated. The cell was fabricated and measured in TSMC 65nm technology with a highly competitive area of 1420F2 per bit.

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DO - https://doi.org/10.1109/ISCAS.2019.8702612

M3 - منشور من مؤتمر

T3 - Proceedings - IEEE International Symposium on Circuits and Systems

BT - 2019 IEEE International Symposium on Circuits and Systems, ISCAS 2019 - Proceedings

PB - Institute of Electrical and Electronics Engineers Inc.

T2 - 2019 IEEE International Symposium on Circuits and Systems, ISCAS 2019

Y2 - 26 May 2019 through 29 May 2019

ER -

Shifman Y, Miller A, Weizman Y, Fish A , Shor J. An SRAM PUF with 2 independent bits/cell in 65nm. In 2019 IEEE International Symposium on Circuits and Systems, ISCAS 2019 - Proceedings. Institute of Electrical and Electronics Engineers Inc. 2019. 8702612. (Proceedings - IEEE International Symposium on Circuits and Systems). doi: https://doi.org/10.1109/ISCAS.2019.8702612

An SRAM PUF with 2 independent bits/cell in 65nm

Abstract

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Keywords

All Science Journal Classification (ASJC) codes

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